I want to connect our own custom board (with four ad9695 chips on it) to a zcu102 via fmc connectors and use IIO-Oscillioscope to capture the data from all links.
However, I checked p.25 of the zcu102 datasheet, the highest memory bandwidth that PS-DDR can provide is 17.6 GB/s. For our design, we need to receive all the data from four AD9695s with sampling rate of 1.25 GSPS. For each sample representing 16 bits (2 bytes) data, we need the memory bandwidth to be larger than 4*2*1.25G*2 = 20 GB/s, so we need to find out other ways to deal with this high-speed data.
Could you give me any possible solution for this? For example, the possibilty to also use PL-DDR, or use the on-chip memory? Or any similar fpga design would also be helpful!
I saw your employee also propose a possible solution for a similar case. But I'm not sure if that is possible for case.
Thanks in advance!