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Four AD9695 on single ZCU102, Memory bandwidth problem

Category: Hardware
Product Number: AD9695


I want to connect our own custom board (with four ad9695 chips on it) to a zcu102 via fmc connectors and use IIO-Oscillioscope to capture the data from all links.

However, I checked p.25 of the zcu102 datasheet, the highest memory bandwidth that PS-DDR can provide is 17.6 GB/s. For our design, we need to receive all the data from four AD9695s with sampling rate of 1.25 GSPS. For each sample representing 16 bits (2 bytes) data, we need the memory bandwidth to be larger than 4*2*1.25G*2 = 20 GB/s, so we need to find out other ways to deal with this high-speed data.

Could you give me any possible solution for this? For example, the possibilty to also use PL-DDR, or use the on-chip memory? Or any similar fpga design would also be helpful!

I saw your employee also propose a possible solution for a similar case. But I'm not sure if that is possible for case.

Thanks in advance!

  • Hello  ,

    Just letting you know that someone saw your thread and will assist you in a couple of days.

    In the meantime, if you have any updates or more information, please let us know.

    Best regards,

  • Ok, thanks for your support.

    Look forward to hearing you back.

  • Hello,

    If I understand correctly, you need to offload data from 16 transceivers running at 12.5Gbps.

    The PL DDR for ZCU102 is 16 bits wide so it won't give you enough bandwidth for your use case.

    In our designs, we use the data offload module with BRAM as storage. hdl/ad9081_fmca_ebz_bd.tcl at master · analogdevicesinc/hdl ( can be used as an example. You'll probably be very limited at the number of samples you can capture and still pass timing.

    I think using UltraRAM may be an alternative, but we don't have support for it.



  • Hi Adrian,

    Thanks for your reply! Just want to make sure: Can't we use both PS DDR and PL DDR simultaneously by using 2 DMA controllers to receive all of the data to memory?

  • Hello,

    We don't have an example of that, but in theory we have sync start option on the DMA so they should be able to transfer data. We've validated multi FPGA sync using this option so that works.

    We are using the HP ports which have a maximum throughput of 330MHz@128bits which should cover one AD9695, which we use in our reference design. If you use two of the HP ports, it's possible that it would work but would need to be tested in hardware.  I highly doubt 3 would work without losing data, but in theory it can be possible.

    The PL DDR, with 16 x 2 x 2400 would give an interface of 300MHzx 256 bits which would not suffice for two AD9095 even at 100% efficiency of writing to the DDR(i'm not even sure if the PL DDR works at 2400, maybe slightly lower, as we don't use it in our design).