Hello.
I currently have a ZCU102 with an AD9986 board operating with 122.88 MHz as the main reference.
The HMC7044 on the AD9986 board is running with a PLL2 frequency of 3000 MHz.
The 3000 MHz is then used to create all clocks with 3000/12 generating 250 MHz for the DAC.ADC.
The AD9986 uses the 250 MHz reference to run at 12 GHz for the DAC and 6 GHz for the ADC.
I want to run all clocks as integer multiples from the 122.88 MHz, so I changed the HMC7044 PLL2 frequency from 3000 MHz to 2949.12 MHz.
Doing this makes the AD9986 DAC/ADC reference run at 245.76 MHz, and the DAC/ADC should be running at 11796.48 MHz and 5898.24 MHz.
Unfortunately, this change breaks the system where the rx and tx devices cannot be seen.
Running jesd_status shows the correct rate for the link clock at 245.76 MHz but the JESD lanes are not working.
When I use iio_oscilloscope, the rx and tx devices cannot be seen. These can be seen with an unedited dts file.
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The dts file has the following lines.
adi,dac-frequency-hz = < 0x02 0xcb417800 >;
adi,adc-frequency-hz = < 0x01 0x65a0bc00 >;
These values equate to 3410065408 Hz and 1705032704 Hz which do not seem to relate to anything.
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When I look at HMC7044 register values for channel dividers with the unedited dts file, I noticed that the values that I read from iio_oscilloscope do not all match the values defined in the dts file.
It looks like something in the system is making the values change.
If I do the same thing with the edited file (3000 MHz -> 2949.12 MHz), the channel divider values match between the dts file and those read from iio_oscilloscope.
Any help to make this work would be much appreciated.
