ADRV9364-z7020 in ADRV1CRR-FMC

Hi Luke.

First step would be to rebuild the design for your FPGA part by modifying this line.

Checking that the package you want to select has the same pin locations or requires small changes in schematic/layout, it is totally up to you.

Andrei

Hi Luke.

First step would be to rebuild the design for your FPGA part by modifying this line.

Checking that the package you want to select has the same pin locations or requires small changes in schematic/layout, it is totally up to you.

Andrei

Hi Andrei,

So, I would need to edit the .xdc files for the pins I want to change?

Is there no example project of someone doing this?

Luke

Hi,

LukeDy said:

So, I would need to edit the .xdc files for the pins I want to change?

Yes.

LukeDy said:

Is there no example project of someone doing this?

I'm not aware of any.

Andrei

Andrei, I spent a good part of yesterday trying to edit the .xdc files to get a working image. I also went into the BD in Vivado and removed a bunch of the IP, like HDMI, that I won't be using. Is there no way to just add ethernet support to the example BOB project for the z7020? They have a common pinning for the ethernet PHY. It just would seem to be much cleaner since I only need linux running a shell over ethernet.

Luke

LukeDy said:

Is there no way to just add ethernet support to the example BOB project for the z7020? They have a common pinning for the ethernet PHY. It just would seem to be much cleaner since I only need linux running a shell over ethernet.

The ADI designs for adrv9361z7035 and adrv9364z7020 both have ethernet connections in our reference design. The eth phy is directly connected to the zynq mio's.
That is all. no separate license needed for ethernet. 

Andrei

Hi Andrei,

I am trying to work from ../hdl/projects/adrv9364z7020 (or z7035) and using vivado. When I scrutinize the XDC for the z7020 I do not see any ethernet parameters or pins called out. I want to use the PHY on the card. Is this just a constraint that Vivado knows to apply for this device? I really would like some clear instructions on how to build the z7020 image ensuring ethernet is included. Right now, in Vivado, I see no indication that ethernet is being included in the design. Am I missing something?

Thank you,

Luke

Andrei,

I believe I have figured this out. The key is Vivado (and more specifically the Zynq IP) configures the "fixed" IO from its own knowledge of each device. When I look at the output of the z7020 example that can be built I see my ethernet pins are completely routed to MIO "fixed IO" pins and are consistent with my schematic for the PHY interface. These are then consistent with the IP configuration tool in Vivado for the Zynq. I appreciate all of your help, but this seems very clear now.

Luke