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AD9361 DAC Multi Tone Wave Generation With Default IP

Category: Software
Product Number: AD9361
Software Version: FSCOMMS2

Hello everyone,

I'm working on a design with AD9361 and Zedboard. I was able to run the SAMPLE project designed in Ad9361 in the name_HDL. I work for no-os. I have a few questions about AD9361 IP;
1- What I want to do in my design is actually to print the signs of different frequencies I produce in numerical design. All I need is the 16bit input pin that I will enter the I and Q channels on IP. But it seems to have your own DDS on the IP. Although I do DDS_DISABLE 1, I see that sign on what I just entered into the tx_lo_en value at the txout. What do you think I should do?
2- I want to be able to take the signs produced in different tones and process those signs in different tones using the AD9361's download. But now I can't see ADC Raw Data with ILA. How can I correct this situation?

As you can see for the DAC, I produce signs at 2 different frequency and enter the dac_datai and q pins of the AD9361 IP. I want to do the signs of 3 and 5mhz with tx_lo and see it in TXout.
For example tx_lo = 2400MHz
Two tone = 3mhz and 5 MHz
tx_out = 2403MHz and 2405mhz or 2397mhz and 2395mhz


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  • Hello  

    Thanks for reply. I was able to produce multitone signals. I was able to run the ADC as well. But I have detailed observations in 2 subjects. I want to share it with you;

    1) I applied 2 different tones to the DAC at 8.8MHZ and 8.9MHZ 100khz intervals. On the spectrum it appears in two tones. But the RF output powers are very, very low. In addition, the DAC NCO frequency appears in the spectrum as it is. This is disturbing. I'm used to having DC offsets in DACs, but I couldn't eliminate the NCO here. Do you have a suggestion about it? In addition, the signal I produced from DDS's is a 12bit signal. SFDR 72db. When I increase the DDS SFDRs to 96db (16bit DDS resolution) I see an increase in gains in my spectrum but still not enough. It rises to about -43dbm. When I turned my attenetors completely down, I was able to reach the maximum -33dbm levels. I can't seem to make full use of the DAC's dynamic range. The spectrum image is below. 

    2) In my tests for the ADC, I applied 2401MHZ and 20403MHZ signals and examined its FFT. My RX bandwidth was set to 5MHZ in these reviews. ADC lo was installed at 2400MHZ. Although the ADC signals appear to be clean, I saw some offsets when I examined the frequencies in the FFTs. I have observed that these offsets increase as the frequency increases.  The Matlab screenshot is below. 

    The first solution ideas that come to my mind are;

    - Connecting a smooth 40MHZ clock instead of the 40MHZ clock on FMCOMMS2. I think the reason for the frequency offsets in the ADC is the 40MHZ reference clock.
    - I can't comment on the output gain on the DAC. I just think there should be hardware touches on the eval board.

    I am waiting for your support.