AD9361 DAC Multi Tone Wave Generation With Default IP

Hello FarukS ,

Just confirming that we saw your thread and someone will attend to your questions in the next couple of days.

Best regards,
Iulia

Hello iulia 

Thanks for reply. I was able to produce multitone signals. I was able to run the ADC as well. But I have detailed observations in 2 subjects. I want to share it with you;

1) I applied 2 different tones to the DAC at 8.8MHZ and 8.9MHZ 100khz intervals. On the spectrum it appears in two tones. But the RF output powers are very, very low. In addition, the DAC NCO frequency appears in the spectrum as it is. This is disturbing. I'm used to having DC offsets in DACs, but I couldn't eliminate the NCO here. Do you have a suggestion about it? In addition, the signal I produced from DDS's is a 12bit signal. SFDR 72db. When I increase the DDS SFDRs to 96db (16bit DDS resolution) I see an increase in gains in my spectrum but still not enough. It rises to about -43dbm. When I turned my attenetors completely down, I was able to reach the maximum -33dbm levels. I can't seem to make full use of the DAC's dynamic range. The spectrum image is below. 

2) In my tests for the ADC, I applied 2401MHZ and 20403MHZ signals and examined its FFT. My RX bandwidth was set to 5MHZ in these reviews. ADC lo was installed at 2400MHZ. Although the ADC signals appear to be clean, I saw some offsets when I examined the frequencies in the FFTs. I have observed that these offsets increase as the frequency increases.  The Matlab screenshot is below. 

The first solution ideas that come to my mind are;

- Connecting a smooth 40MHZ clock instead of the 40MHZ clock on FMCOMMS2. I think the reason for the frequency offsets in the ADC is the 40MHZ reference clock.
- I can't comment on the output gain on the DAC. I just think there should be hardware touches on the eval board.

I am waiting for your support.

Sincelery

Hi,

Sorry for the delayed reply!

FarukS said:

I see that sign on what I just entered into the tx_lo_en value at the txout. What do you think I should do?

Can you elaborate? Is not clear to me what are you entering/expecting here.

FarukS said:

2- I want to be able to take the signs produced in different tones and process those signs in different tones using the AD9361's download. But now I can't see ADC Raw Data with ILA. How can I correct this situation?

Are you running Kuiper(Linux) or no-OS on zed board? Ether way I'm interested in the messages from system power-on. If the there are any issues in initializing any components regarding ad9361.
If you probe the signals coming out of the adc_fifo there shouldn't be any problem in capturing signals with an ILA.
My recommendation is to capture the samples and move them on your machine. This gives you a higher sample count and probably speed, comparing with an ILA.
On linux use IIO-Oscilloscope or pyadi-iio.
On no-OS. IIO-Osc or set a big buffer(RAM) and move data over JTAG, there are a few threads regarding this on EZ, let me know if you need help finding those, if it is the case.

FarukS said:

As you can see for the DAC, I produce signs at 2 different frequency and enter the dac_datai and q pins of the AD9361 IP. I want to do the signs of 3 and 5mhz with tx_lo and see it in TXout.
For example tx_lo = 2400MHz
Two tone = 3mhz and 5 MHz
tx_out = 2403MHz and 2405mhz or 2397mhz and 2395mhz

This can be done very easily on the reference design using the IIO-Oscilloscope, If you only intend to do this frequency tests.
There is an independent IQ control that lets you play with this parameters of the internal DDS(axi_ad9361 from hdl).

FarukS said:

When I increase the DDS SFDRs to 96db (16bit DDS resolution) I see an increase in gains in my spectrum but still not enough. It rises to about -43dbm. When I turned my attenetors completely down, I was able to reach the maximum -33dbm levels. I can't seem to make full use of the DAC's dynamic range. The spectrum image is below. 

The data going to the dac is MSB aligned, meaning yout of the 16bits only the upper 12 will be used. in your case, probably the lower 4 bits where dropped. See the DATA description https://wiki.analog.com/resources/fpga/docs/axi_ad9361#internal_interface_description

https://ez.analog.com/fpga/f/q-a/84670/eliminating-ad9361-tx-carrier-output-dc-output

FarukS said:

I have observed that these offsets increase as the frequency increases. 

https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/hardware/card_specification

https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/hardware/tuning

Andrei

Hello FarukS ,

Do you have any updates?

Regards,
Iulia

Closed due to inactivity