Category: Software
Product Number: AD9656
Software Version: Xilinx Vivado 2019.1
hello.
I'm trying to acquire data using 3 AD9656 ADCs and a Zynq UltraScale+ FPGA.
I configured Multi-link using the "adi_xcvr" and "ADI JESD204 Receive" IP Cores of ADI Reference Design.
A total of 12 Lanes and 3 Links operate normally.
The data width output from the link layer is 384 bits, but I don't know how to set the parameters of the transport layer to connect it.
I think the L and M values of the Transport Layer should be set to 12. However, the available L values are 1,2,4,8,16 and the M values are 1,2,4,6,8,16,32,64.
I understand that TPL is needed to deframe the framed data input from the link layer.
Please tell me how to set TPL in the same configuration as mine.
Also, please let me know if there are any mistakes in the link configuration.
Below is the current design block diagram.
Link status and Lane status log files are attached.
AD9656[0] setup success
AD9656[1] setup success
AD9656[2] setup success
AD9656[3] setup success
ad9656_xcvr_0: OK (2048000 kHz)
ad9656_jesd_0 status:
Link is enabled
Measured Link Clock: 51.201 MHz
Reported Link Clock: 51.200 MHz
Lane rate: 2048.000 MHz
Lane rate / 40: 51.200 MHz
LMFC rate: 3.200 MHz
Link status: DATA
SYSREF captured: Yes
SYSREF alignment error: No
ad9656_jesd_0 lane 0 status:
Errors: 0
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 3 Multi-frames and 34 Octets
Initial Lane Alignment Sequence: Yes
DID: 192, BID: 0, LID: 0, L: 4, SCR: 1, F: 2
K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
FCHK: 0x7, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
FC: 2048000 kHz
ad9656_jesd_0 lane 1 status:
Errors: 0
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 3 Multi-frames and 35 Octets
Initial Lane Alignment Sequence: Yes
DID: 192, BID: 0, LID: 1, L: 4, SCR: 1, F: 2
K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
FCHK: 0x8, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
FC: 2048000 kHz
ad9656_jesd_0 lane 2 status:
Errors: 0
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 3 Multi-frames and 34 Octets
Initial Lane Alignment Sequence: Yes
DID: 192, BID: 0, LID: 2, L: 4, SCR: 1, F: 2
K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
FCHK: 0x9, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
FC: 2048000 kHz
ad9656_jesd_0 lane 3 status:
Errors: 0
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 3 Multi-frames and 37 Octets
Initial Lane Alignment Sequence: Yes
DID: 192, BID: 0, LID: 3, L: 4, SCR: 1, F: 2
K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
FCHK: 0xA, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
FC: 2048000 kHz
ad9656_jesd_0 lane 4 status:
Errors: 0
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 3 Multi-frames and 34 Octets
Initial Lane Alignment Sequence: Yes
DID: 192, BID: 0, LID: 0, L: 4, SCR: 1, F: 2
K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
FCHK: 0x7, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
FC: 2048000 kHz
ad9656_jesd_0 lane 5 status:
Errors: 0
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 3 Multi-frames and 36 Octets
Initial Lane Alignment Sequence: Yes
DID: 192, BID: 0, LID: 1, L: 4, SCR: 1, F: 2
K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
FCHK: 0x8, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
FC: 2048000 kHz
ad9656_jesd_0 lane 6 status:
Errors: 0
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 3 Multi-frames and 36 Octets
Initial Lane Alignment Sequence: Yes
DID: 192, BID: 0, LID: 2, L: 4, SCR: 1, F: 2
K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
FCHK: 0x9, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
FC: 2048000 kHz
ad9656_jesd_0 lane 7 status:
Errors: 0
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 3 Multi-frames and 34 Octets
Initial Lane Alignment Sequence: Yes
DID: 192, BID: 0, LID: 3, L: 4, SCR: 1, F: 2
K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
FCHK: 0xA, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
FC: 2048000 kHz
ad9656_jesd_0 lane 8 status:
Errors: 0
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 3 Multi-frames and 37 Octets
Initial Lane Alignment Sequence: Yes
DID: 192, BID: 0, LID: 0, L: 4, SCR: 1, F: 2
K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
FCHK: 0x7, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
FC: 2048000 kHz
ad9656_jesd_0 lane 9 status:
Errors: 0
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 3 Multi-frames and 35 Octets
Initial Lane Alignment Sequence: Yes
DID: 192, BID: 0, LID: 1, L: 4, SCR: 1, F: 2
K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
FCHK: 0x8, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
FC: 2048000 kHz
ad9656_jesd_0 lane 10 status:
Errors: 0
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 3 Multi-frames and 35 Octets
Initial Lane Alignment Sequence: Yes
DID: 192, BID: 0, LID: 2, L: 4, SCR: 1, F: 2
K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
FCHK: 0x9, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
FC: 2048000 kHz
ad9656_jesd_0 lane 11 status:
Errors: 0
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 3 Multi-frames and 34 Octets
Initial Lane Alignment Sequence: Yes
DID: 192, BID: 0, LID: 3, L: 4, SCR: 1, F: 2
K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
FCHK: 0xA, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
FC: 2048000 kHz
Thanks,
