How is Sysref (JESD204B class 1) used in FPGA?

Hello dgun ,

1. In the majority of ADI designs the SYSREF signal comes from a clock distribution chip(for example HMC7044) from the device that is connected to the FPGA through an FMC connector, which means most of the time, SYSREF is an input to the FPGA, both jesd_tx and jesd_rx cores expect SYSREF as an input. For JESD204B subclass 1, in order to obtain deterministic latency, SYSREF frequency has to be a submultiple of LMFC, but this is very specific to the device you are using so more details about the SYSREF timing requirements can be found in the User Guide of the converter/chip you want to use. The SYSREF frequency is usually set in the software in a devicetree or config file where the clock chip is configured. From an FPGA point of view the only timing constraint that you would want for the SYSREF is to be edged aligned with the device clocks(https://github.com/analogdevicesinc/hdl/blob/master/projects/ad9081_fmca_ebz/vcu118/timing_constr.xdc#L44), but this is a requirement for newer designs where JESD204C comes in place, so higher lane rates are needed and less errors are accepted. If you want to find out how the SYSREF signal is used in our JESD core you can take a look to this overview from wiki: https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_rx.
2. When you want to generate the SYSREF from the FPGA(SYSREF is an output) you can use this module https://github.com/analogdevicesinc/hdl/blob/master/library/common/ad_sysref_gen.v which is basically a frequency divider of a used device clock.
3. The lane rate/40 gives you the link_clock=device_clock frequency, you can see how those frequencies are computed in the timing_constr.xdc file from the first link.

Let me know if you have any other questions!

Best regards,

Filip

Hello dgun ,

1. In the majority of ADI designs the SYSREF signal comes from a clock distribution chip(for example HMC7044) from the device that is connected to the FPGA through an FMC connector, which means most of the time, SYSREF is an input to the FPGA, both jesd_tx and jesd_rx cores expect SYSREF as an input. For JESD204B subclass 1, in order to obtain deterministic latency, SYSREF frequency has to be a submultiple of LMFC, but this is very specific to the device you are using so more details about the SYSREF timing requirements can be found in the User Guide of the converter/chip you want to use. The SYSREF frequency is usually set in the software in a devicetree or config file where the clock chip is configured. From an FPGA point of view the only timing constraint that you would want for the SYSREF is to be edged aligned with the device clocks(https://github.com/analogdevicesinc/hdl/blob/master/projects/ad9081_fmca_ebz/vcu118/timing_constr.xdc#L44), but this is a requirement for newer designs where JESD204C comes in place, so higher lane rates are needed and less errors are accepted. If you want to find out how the SYSREF signal is used in our JESD core you can take a look to this overview from wiki: https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_rx.
2. When you want to generate the SYSREF from the FPGA(SYSREF is an output) you can use this module https://github.com/analogdevicesinc/hdl/blob/master/library/common/ad_sysref_gen.v which is basically a frequency divider of a used device clock.
3. The lane rate/40 gives you the link_clock=device_clock frequency, you can see how those frequencies are computed in the timing_constr.xdc file from the first link.

Let me know if you have any other questions!

Best regards,

Filip

Thank you. What I take from this is that the lane rate/40 clocks are the equivalent of device clocks for the FPGA, so they need to be aligned with the corresponding sysref.