I understand the requirement for devices where sysref and device clock must be source synchronous and sysref must meet setup and hold timing to device clock. Also, all devices to be synchronized must have length matched sysrefs (or be adjustable from clock distribution point). However, what is the requirement for the sysref going to the FPGA? Nothing I have found so far discusses the timing requirements of the FPGA sysref. Let's say, for example, that I have two identical JESD204B ADCs with identical configuration. I length match the adc0_sysref, adc0_deviceclock, adc1_sysref, and adc1_deviceclock. The sysrefs and device clocks are all coming from a source-synchronous clock distribution device. The literature says I also need a sysref and lane rate/40 signal going to the FPGA. What are the timing requirements, if any, of the sysref signal going to the FPGA compared to the sysref signals going to the ADCs? How is the sysref signal going to the FPGA used? What is the timing requirement, if any, of the sysref signal going to the FPGA and the lane rate/40 signal going to the FPGA?
