Dear,
We have an AD9082-FMCA-EBZ evaluation board which is functional with a Xilinx ZCU102 FPGA board.
In our setup, we have used the HDL reference design and the Petalinux device tree “zynqmp-zcu102-rev10-ad9082-m4-l8.dts”.
The HDL reference is slightly modified so we can feed the DAC0 with a DC-valued signal (both I and Q channels).
We intended to measure the DAC’s phase noise performance, however we noticed that the generated tone is not stable and varies multiple kilo Hertz.
Figure 1 shows the generated tone when the main NCO is set to 1.2Hz and in Figure 2 the NCO is set to 4GHz.
To visualize the frequency variation, the spectrum analyzer is set to max hold for 5 seconds, the span is 10KHz and the resolution bandwidth is 10Hz.
We also investigated the clock MxFE Clkin (250MHz) which is produced by CH2 of HMC7044. We observed a spurious at 22.667KHz from the main component (Figure 3). Moreover, the same frequency instability is obvious on this 250MHz clock (Figure 4) as well as the 100MHz crystal oscillator (Figure 5). The measurement was performed at Y1B, so it refers to the VECTRON VCC6-LAB-100M connected to CLKIN0 of HMC7044.
We couldn’t get a clean phase noise measurement due to this frequency instability, and the expected level is far from expectations.
Do you think the evaluation board could be defective or what could be the cause?
