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Unstable single tone generation by AD9082

Category: Hardware


We have an AD9082-FMCA-EBZ evaluation board which is functional with a Xilinx ZCU102 FPGA board.

In our setup, we have used the HDL reference design and the Petalinux device tree “zynqmp-zcu102-rev10-ad9082-m4-l8.dts”.

The HDL reference is slightly modified so we can feed the DAC0 with a DC-valued signal (both I and Q channels).

We intended to measure the DAC’s phase noise performance, however we noticed that the generated tone is not stable and varies multiple kilo Hertz.

Figure 1 shows the generated tone when the main NCO is set to 1.2Hz and in Figure 2 the NCO is set to 4GHz.

To visualize the frequency variation, the spectrum analyzer is set to max hold for 5 seconds, the span is 10KHz and the resolution bandwidth is 10Hz.

We also investigated the clock MxFE Clkin (250MHz) which is produced by CH2 of HMC7044. We observed a spurious at 22.667KHz from the main component (Figure 3). Moreover, the same frequency instability is obvious on this 250MHz clock (Figure 4) as well as the 100MHz crystal oscillator (Figure 5). The measurement was performed at Y1B, so it refers to the VECTRON VCC6-LAB-100M connected to CLKIN0 of HMC7044.

We couldn’t get a clean phase noise measurement due to this frequency instability, and the expected level is far from expectations.

Do you think the evaluation board could be defective or what could be the cause?


The issue may be associated with HMC7044's  PLL1 not locking hence causing frequency drift of the reference that drives PLL2.

Perhaps best to bypass HMC7044 and drive the CLKIN input directly with high quality, low phase noise RF generator.  This will require rotating the 0402 capacitors that located between the CLK balun and AD9082 device input.  Since this balun is meant to pass signals between 3-12 GHz.........suggest driving it with a CLK frequency that is 4x the MxFE's intended PFD frequency.   For example, one may target a PFD of 500 or 750 MHz to get best phase noise from on-chip PLL hence on can drive with external RF generator with input frequency of 2 GHz or 3 GHz (which gets divided down by R-divider of on-chip PLL).  When using an external will also need to provide the REFCLK to the ADS9V2 board's SMA connector (EXT CLK on corner of board) with a 2nd RF generator that is locked to the 1st RF generator providing the CLKIN input (use 10 Mhz REFIN/OUT on generators back panel).  One may also consider locking the spectrum analyzer to the same 10 MHz reference so absolutely no frequency drift can occur.

Lastly, one may 1st consider electing to evaluate phase noise with NCO tuned to exactly FDAC/4 (DC inputs for I/Q inputs with value of 22300).  No spurious should be evident in spectrum since all odd and even harmonics should fall at multiples of N*FDAC/4.

  • Thanks for your reply. Using an external clock generator to drive the MxFE is not a plug-and-play solution as we need to change the FPGA design as well as the petalinux devicetree to connect the evaluation board to the other FMC connector of the ZCU102 board. You can see my previous ticket here:

    Meanwhile, I managed to repeat the experiment with a clean external 100MHz clock to drive the HMC7044 (through HMC external clock connector). You can see the DAC output at 750MHz for both cases (with/without external HMC ref clock). It's still far away from the point where we can measure the phase noise performance.

    Fig 1. Max hold on DAC output at 750MHz, with the onboard HMC ref

    Fig 2. Max hold on DAC output at 750MHz, with an external HMC ref.

    If there is any problem with the clocking chips and onboard modules, how we can request a repair?

  • FormerMember
    0 FormerMember on May 18, 2023 3:19 PM in reply to SAH


    Has this issue been resolved when applying a stable 100 MHz external RF clock to the EXT HMC REF sma connector.and using ACE clock configuration as shown below?

  • Hi, 

    Yes. We applied an external 100MHz clock to the HMC reference connector. We also had to modify the device tree slightly as the second HMC reference clock is set to 10MHz in the original device tree. Also, we remove the E1B ferrite to ensure the internal oscillator is disabled.