AD9363 with Zynq7010 or pluto sdr data line directly with PL

Question

Hi, I am planning to control AD9363 chip or configure with PS side in No-OS mode while providing it IQ samples or TX data from PL side. Is it really possibly, If yes How? I have been able to initialize the AD9363 of Pluto using Zynq No-OS mode but i want to by-pass all the DMA's etc to directly provide data samples to AD9363. Thankyou!

andrei_g · Answer

It is not 100% clear to us if you want to use the PS or not. To be clear. Configuring the AD9361(SPI) or axi_ad9361(axi) from a PL state machine is not supported in our designs. Thing will get way too complicated with a PL state machine for AD9361 config. So the system configurations is done by zynq PS. 
 Waleed said: i want to hand over the data directly to the chip from PL side. 
 This is what the DDS(from PL) is doing. The waveforms are generated in hdl after a PS configures the DDS parameters. You can replace the DMA with your custom logic that sends data directly to the axi_ad9361, for this you have to select the the axi_ad9361's dma port as a source, in channel register REG_CHAN_CNTRL_7( 0x0418). There is a function in no-OS for this. https://wiki.analog.com/resources/fpga/docs/axi_dac_ip#register_map axi_ad9361 always sends data to the AD9361 in a normal operation mode(after configuration/bring up). 
 Waleed said: Also please let me know that what will be the delay of TX if i for example lets say want to turn on and off the carrier for 1us. there will be some extra dela lets sat 1us+some delay, what would this delay be? 
 The carrier frequency or the whole system as a carrier? For the system, I'm not aware of this type of tests. For carrier frequency take a look at the following threads: RE: AD9364 - Tx/Rx LO Frequency Change Settling Time How to decrease the AD9361 LO tuning Time RE: AD9361 Lo Freqency Setting Configuring LO in AD9361 RE: AD9361 - LO frequency changes Andrei

andrei_g · Answer

As I said, the design can be used for what you need. Connect your logic instead of the dma(axi_dmac, pack). Take a look at: RE: ADRV9361-Z035 inserting custom IP into HDL reference design Transciever toolbox, custom block and AD9361, No OS QPSK-modem example https://wiki.analog.com/resources/fpga/docs/hdl/fmcomms2_fir_filt 
 Andrei

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AD9363 with Zynq7010 or pluto sdr data line directly with PL