AD9363 with Zynq7010 or pluto sdr data line directly with PL

Hello Waleed ,

Ok, so through DDS. Then you can take a look at this page https://wiki.analog.com/resources/fpga/docs/axi_dac_ip containing the register map for the AXI DAC IP core. The sections that interest you are "DAC channel" and "DAC common".

First, make sure that the DDS_DISABLE parameter from the IP's code is set to 0, such that DDS is enabled.

Take the base address from the Address Editor from Vivado or from your No-OS project.
To this base address, you must add 0x4000 for each address mentioned in the example below.
To access a register from this channel (base addr + 0x4000) you add the values from the Address > Byte column from the previous link.

E.g., to write into DAC_DDS_SEL register of channel 0, you write to (base addr  + 0x4000 + 0x418) address.

To have the DDS option selected, you must write 0x0 at (base addr  + 0x4418).

Afterwards, you have to set the DDS registers according to what you're trying to achieve.

An example would be:

• check RSTN register to make sure it's not in reset (REG_RSTN[0])
• see the status (REG_STATUS3)
• set the internal data source to be DDS (REG_CHAN_CNTRL_7)
• set the DDS scale (REG_CHAN_CNTRL_1)
• set the DDS phase initialization and increment (REG_CHAN_CNTRL_2, according to the formula)
• see the status (REG_STATUS3)
• write the clock frequency (REG_STATUS1)
• write the clock ratio (REG_STATUS2)
• synchronise the channels from the DAC after doing all the needed settings (REG_CNTRL_1[0] = 0x1, from "DAC common")

Let me know if this doesn't answer your questions.

Regards,
Iulia

Hello Waleed ,

Ok, so through DDS. Then you can take a look at this page https://wiki.analog.com/resources/fpga/docs/axi_dac_ip containing the register map for the AXI DAC IP core. The sections that interest you are "DAC channel" and "DAC common".

First, make sure that the DDS_DISABLE parameter from the IP's code is set to 0, such that DDS is enabled.

Take the base address from the Address Editor from Vivado or from your No-OS project.
To this base address, you must add 0x4000 for each address mentioned in the example below.
To access a register from this channel (base addr + 0x4000) you add the values from the Address > Byte column from the previous link.

E.g., to write into DAC_DDS_SEL register of channel 0, you write to (base addr  + 0x4000 + 0x418) address.

To have the DDS option selected, you must write 0x0 at (base addr  + 0x4418).

Afterwards, you have to set the DDS registers according to what you're trying to achieve.

An example would be:

• check RSTN register to make sure it's not in reset (REG_RSTN[0])
• see the status (REG_STATUS3)
• set the internal data source to be DDS (REG_CHAN_CNTRL_7)
• set the DDS scale (REG_CHAN_CNTRL_1)
• set the DDS phase initialization and increment (REG_CHAN_CNTRL_2, according to the formula)
• see the status (REG_STATUS3)
• write the clock frequency (REG_STATUS1)
• write the clock ratio (REG_STATUS2)
• synchronise the channels from the DAC after doing all the needed settings (REG_CNTRL_1[0] = 0x1, from "DAC common")

Let me know if this doesn't answer your questions.

Regards,
Iulia