AD9363 with Zynq7010 or pluto sdr data line directly with PL

Hello,

First of all, what design are you using as a starting point?

Regards,
Iulia

To answer your questions:

1. Yes, that's exactly how we use it. It is controlled from the PS side and the data is sent through the PL. That's how it's implemented in Pluto also.
2. We don't have support for Pluto in No-OS, but you can port it. Starting from the design for AD-FMCOMMS2, you can tweak it a bit to match your requirements. If you need help with this further, ask on the Microcontroller No-OS drivers forum -- they can help you with it.
3. What does "bypass all the DMA's etc to directly provide data samples to AD9363" mean? How are you planning on sending the samples without using the DMA?

Regards,
Iulia

1. I am using the project files of hdl provided within the github repository. I want to change that design at some point,

2. I am able to initialise AD9363 from PS, but yes more things needs to be sorted out.

3. for example i want to transmit Sine wave, i want to use DDS core in PL side or built in vivado DDS IP core in IF and then i want to give these IQ samples to AD9361 without involvment of DDR/RAM, a custom RAM/Register could e use for storing the samples but not the shared RAM,  so that it can be transmitted over the frequency we have set through PS.

Thank you very much for the help.

Hello Waleed ,

Ok, so through DDS. Then you can take a look at this page https://wiki.analog.com/resources/fpga/docs/axi_dac_ip containing the register map for the AXI DAC IP core. The sections that interest you are "DAC channel" and "DAC common".

First, make sure that the DDS_DISABLE parameter from the IP's code is set to 0, such that DDS is enabled.

Take the base address from the Address Editor from Vivado or from your No-OS project.
To this base address, you must add 0x4000 for each address mentioned in the example below.
To access a register from this channel (base addr + 0x4000) you add the values from the Address > Byte column from the previous link.

E.g., to write into DAC_DDS_SEL register of channel 0, you write to (base addr  + 0x4000 + 0x418) address.

To have the DDS option selected, you must write 0x0 at (base addr  + 0x4418).

Afterwards, you have to set the DDS registers according to what you're trying to achieve.

An example would be:

• check RSTN register to make sure it's not in reset (REG_RSTN[0])
• see the status (REG_STATUS3)
• set the internal data source to be DDS (REG_CHAN_CNTRL_7)
• set the DDS scale (REG_CHAN_CNTRL_1)
• set the DDS phase initialization and increment (REG_CHAN_CNTRL_2, according to the formula)
• see the status (REG_STATUS3)
• write the clock frequency (REG_STATUS1)
• write the clock ratio (REG_STATUS2)
• synchronise the channels from the DAC after doing all the needed settings (REG_CNTRL_1[0] = 0x1, from "DAC common")

Let me know if this doesn't answer your questions.

Regards,
Iulia

Hello Waleed ,

Do you have any updates? Did my last reply answer your questions?

Regards,
Iulia

I was able to transmit using DDS with NO-OS but this not what i intend to do, I actually do not want to involve any component of PS in the design except for the setting of lo_freq etc. or i will just say that the configuration of AD9361, i want to hand over the data directly to the chip from PL side.
I am very thankful for your follow up.
Also please let me know that what will be the delay of TX if i for example lets say want to turn on and off the carrier for 1us. there will be some extra dela lets sat 1us+some delay, what would this delay be?

It is not 100% clear to us if you want to use the PS or not. To be clear. Configuring the AD9361(SPI) or axi_ad9361(axi) from a PL state machine is not supported in our designs. Thing will get way too complicated with a PL state machine for AD9361 config. So the system configurations is done by zynq PS.

Waleed said:

i want to hand over the data directly to the chip from PL side.

This is what the DDS(from PL) is doing. The waveforms are generated in hdl after a PS configures the DDS parameters.
You can replace the DMA with your custom logic that sends data directly to the axi_ad9361, for this you have to select the the axi_ad9361's dma port as a source, in channel register REG_CHAN_CNTRL_7(0x0418). There is a function in no-OS for this.
https://wiki.analog.com/resources/fpga/docs/axi_dac_ip#register_map

axi_ad9361 always sends data to the AD9361 in a normal operation mode(after configuration/bring up).

Waleed said:

Also please let me know that what will be the delay of TX if i for example lets say want to turn on and off the carrier for 1us. there will be some extra dela lets sat 1us+some delay, what would this delay be?

The carrier frequency or the whole system as a carrier?
For the system, I'm not aware of this type of tests. For carrier frequency take a look at the following threads:
RE: AD9364 - Tx/Rx LO Frequency Change Settling Time

How to decrease the AD9361 LO tuning Time

RE: AD9361 Lo Freqency Setting
Configuring LO in AD9361
RE: AD9361 - LO frequency changes

Andrei

andrei_g said:

It is not 100% clear to us if you want to use the PS or not. To be clear. Configuring the AD9361(SPI) or axi_ad9361(axi) from a PL state machine is not supported in our designs. Thing will get way too complicated with a PL state machine for AD9361 config. So the system configurations is done by zynq PS.

My bad i was not able to make it precise, let's say i want to transmit some BPSK modulated signal from ad9363, i want to do all the IF part in PL side without using PS for data path, i can consider using PS for configuration of LO frequency etc but nothing in data path can be involved from PS. So after processing the BPSK in PL i want to directly hand over the modulated data in IF to AD9363.

I hope i am able to put forward my thought clearly.

As I said, the design can be used for what you need. Connect your logic instead of the dma(axi_dmac, pack). Take a look at:
RE: ADRV9361-Z035 inserting custom IP into HDL reference design
Transciever toolbox, custom block and AD9361, No OS
QPSK-modem example
https://wiki.analog.com/resources/fpga/docs/hdl/fmcomms2_fir_filt

Andrei