how to record IQ signals using ad9361z7035

Hello,

Sorry for the delayed reply.

Do you intend to use Linux or No-OS for capturing data?

Regards,

Stanca

hey Stanca! Thank u so much that you replied!

I want to record them on windows operating system however I have created the linux environment using cygwin and have build the hdl refernce design. Now i am confused about how to use the ethernet IP and ad9361z7035 hdl reference design to record the IQ signals! Can u guide me, i shall be highly obliged to you, if i can get any hint from you!

What carrier are you going to use along with the adrv9361z7035?

Besides the HDL design you will need to use software drivers to capture data, and you can choose between Linux drivers or No-OS. 

For more information regarding the design and how to run the software, see adrv9361-z7035 user-guide.

Hey, I am using BOB as carrier. i AM WORKING on OS kuiper image and hdl reference design r2. I want to record IQ signal and want to interface the ethernet IP with adc fifo in vivado. Kindly guide me the step wise procedure. I shall be obliged!

Hi,

The whole hardware/hdl/software stack is there as a reference/example design, you don't have to do anything to the design, just do the setup and capture samples.
Use IIO-Oscilloscope(straight forward) or python to get data on your machine.

Andrei

I dont want to do it via IIOscope. I want to amend the design in a way that I can record and   save the IQ signals for offline use through the HDL design itself. 

Ok, all you need is there...
You will save the samples in the available RAM memory. if you want to save samples in the FPGA's BRAM or some other FPGA resource, think at the size of the storage you need, not that feasible, and the infrastructure is already there.
You can create buffers(in RAM) via the iio framework and get that data later via ethernet or jtag.
Maybe is not clear to us, what do you mean by "save the IQ signals for offline use through the HDL design itself". You have to be more explicit in your posts we are not mentalists.

Andrei

hey sorry for the late reply! 

I dont want to use IIOscope because of its inability to work in a standalone mode. I want a mechanism, where every time the transciever recieves any rf signal, it reads the data, stores it in a file in the form of iq signals for the  later purpose. How can I do this? I also want to analyse the data. So that I can configure whether I should use it directly from the adc output or adc fifo output in vivado. All this I want to do via verilog code.  I hope you got my point now

Hi,

I think I understand what you're trying to achieve.
My guess is that you will need to store big chunks of data from the RF domain. By big I mean, from 2 RF channels you get 4, 12 bits(16bit in memory) I/Q samples.
So, 4 * 16 * 32MSPS = 2Gb just for 1 second. Because of the data throughput, RAM is the best option. If you use smaller sampling rates and decimation filters you will relax the storage requirements.

Also, you probably need an a logic to trigger on the input level or some feature of the signal. This trigger should be use as a starting point/moment in time to store data.
Regarding the storing data based on a trigger m2k should be a good example. The axi_adc_trigger is used in the oscilloscope part of the adalm2000(m2k).
Basically the user can set  a trigger for a certain amplitude/characteristic of the analog signal(rise, fall, e.t.c.). it also controls a  variable fifo, but this is for a "history" feature. to keep part of the samples before the trigger(not of interest to you.
The trigger is used to signal the dma on it's start_sync port that it should start moving samples into memory.

TANZI7702 said:

So that I can configure whether I should use it directly from the adc output or adc fifo output in vivado

Use it from the fifio.
Take a look at https://wiki.analog.com/resources/fpga/docs/hdl/fmcomms2_fir_filt
The fifo is there to move the data from the digital interface(axi_ad9361 - AD9361) clock domain to the device clock domain.
Also look at below licks some of them should be helpful, sorry if I did not filtered them to your need, I'm a bit in a hurry. 
AD937x Rx ADC Triggered Capture with Tx Output (Tx-Rx Loop)

RE: AD9375 External trigger No-OS FPGA reference design
RE: Continuous sample capture with AD9361 and IIO?
RE: AD9361 Data capture using Linux GUI
RE: Synchronizing the ADI AXI DMA to fifo_wr_sync with a AD9467 signal
Storing ADC sample in DDR for further processing
 
Appropriate backend to sample up to 61.44 MSps with no overflow? for AD9361 based platforms

Is this what are you looking for, as a big picture?

Andrei

hey Andrei! Thank you so much for your response! 

I  want to record the signal with 100 MHz bandwidth. According to Nyquist criterion the minimum frequency that I need for fs is 200MHz. However the main problem is that the maximum sampling frequency supported by ad9361z7035 is 61.44MHz. I order to design the decimation  filter I need to set the parameters according to my requirement. So, kindly guide me how can I do away with this issue. 

One more question is that after designing the trigger IP, how can I store the I,Q signal in memory. I am still confused about it. 

Regards

Tanzi