Bitgen Error when changed sampling clock source (l_clk) from axi_ad9361_0 to axi_ad9361_1 in ZC702+FMCOMMS5 hdl_2019_r1 Ref Design

Hello,

Apologies for the delayed reply.

Someone will have a look at this in the next few days.

Until then, do you have any updates that might be relevant for the person assisting you?

Best regards,
Iulia

Thanks for the reply imoldovan 

I can able to generate bitstram by enabling use ssi clk in axi_ad9361 ip customisation.

But still the problem Exists

Sampling Clock (divided clk) from clk axi_clk_div is provided to modem for Modulation and demodulation shows 0 when read back.

Can anyone suggest how to resolve it?

By rebooting or reconfiguring ad9361 gives Clk rate properly .

And Sometimes it shows 0.

Thanks for the reply imoldovan 

I can able to generate bitstram by enabling use ssi clk in axi_ad9361 ip customisation.

But still the problem Exists

Sampling Clock (divided clk) from clk axi_clk_div is provided to modem for Modulation and demodulation shows 0 when read back.

Can anyone suggest how to resolve it?

By rebooting or reconfiguring ad9361 gives Clk rate properly .

And Sometimes it shows 0.

Hi,

Change the reset source for the util_clockdiiv. Use a gpio and a resetgen to sync it to the used clock.
Something does not add up regarding the behavior of your design. Can you do the changes in fmmcomms5_bd.tcl and send us a diff. Following a GUI is not that easy in this case.

Andrei

andrei_g  thanks for the reply.

couldn't able to find the reset circuitry for util_clockdiv in GUI as u said.

i am not getting exactly what changes to be done in fmcomms5_bd.tcl as i am new to TCL concept.

can you help me out with this file?

 https://github.com/analogdevicesinc/hdl/blob/hdl_2019_r1/projects/fmcomms5/common/fmcomms5_bd.tcl

Regards 

sanjuambiger

Hi ambigersanju ,

From Vivado, go to File tab > Export > Export Block Design and send us the system.tcl file that Vivado generates, so we can analyze what connections you've done in your project.

Iulia

Hi imoldovan thanks for the reply.

i have exported system.tcl but couldn't able to upload here as it is showing the file or url is invalid while uploading.

can i paste the full source code here ?

Regards

ambigersanju

hi andrei_g  and imoldovan 

i am using hdl-2019_r1 original  reference design. i have not made any changes to the design.

https://github.com/analogdevicesinc/hdl/tree/hdl_2019_r1/projects/fmcomms5/zc706

just made the divided clock external and i am using it for our Modem Module for mod and demod.

a vhdl code is written to report back the sampled clock which shows 0 sometimes .

our modem is not able to lock when 0 comes instead of 40M.

any ways to troubleshoot this ?

Regards

sanjuambiger

Hi,

ambigersanju said:

i have exported system.tcl but couldn't able to upload here as it is showing the file or url is invalid while uploading.

can i paste the full source code here ?

You can rename it to have a txt extension instead of tcl.

axi_ad9361 has an internal clock monitor. Let's have a look at that too. In no-OS is the message you get on UART with initialized at is the measured interface clock frequency.

This are from master. You might get something slightly different for 2019_r1.

cf-ad9361-lpc: Successfully initialized (122882080 Hz)
ad9361_init : AD936x Rev 2 successfully initialized
cf-ad9361-lpc: Successfully initialized (122882080 Hz)
ad9361_init : AD936x Rev 2 successfully initialized
cf-ad9361-dds-core-lpc: Successfully initialized (122883605 Hz)
cf-ad9361-dds-core-lpc: Successfully initialized (122883605 Hz)
DMA_EXAMPLE: address=0x800000 samples=131072 channels=8 bits=16
Done.

Have a look at this  Fmcomms2 has only one ad9361, same concept. the l_clk(local clock) is used to synchronize the two axi_ad9361, by sourcing the clock from one of them.

ambigersanju said:

just made the divided clock external and i am using it for our Modem Module for mod and demod.

By making it external, you mean you are using it elsewhere. Not that you are using a external clock as the divided clock?
Are you monitoring it with an oscilloscope? is it continuous?
If you are not monitoring it outside the fpga with an oscilloscope. Can you add an ILA(running on the 200MHz clock 1 of the PS) and monitor it with that, jut to see that the clock is continuous?

What messages do you get on UART?

Andrei

Hi andrei_g  thanks for the reply,

following is the method we adapted to make use hdl-2019_r1 design for Modem Development.

diagram shows the part of the bd we have changed.

sorry i couldnt able to draw full diagram , here i am referring to s_clk which is routed to Modem code running in PL.

we can able to bring up the link but s_clk freq read shows 0 sometimes.

as you said i will check the clock wheather it is continuous with ILA as well as with Oscilloscope if possble.

meanwhile is the method adapted is fine ?

Regards 

ambigersanju

ambigersanju said:

meanwhile is the method adapted is fine ?

The data coming from axi_ad9361 is at interface clock, not device clock speed. The interface clock is 4x higher if ad9361 is used in 2R2T mode or 2x higher if used in 1R1T.
Have you kept the fifos in the design between axi_ad9361 and your mod/demod?
https://wiki.analog.com/_detail/resources/fpga/docs/hdl/fmcomms2_fir_2.svg From the link I posted above. In that example we add filters but is can be your IP.

Andrei

andrei_g  as you said we are running AD9361 at 2R2Tmode .

we have not kept any FIFOS in our modem design and we fed divided clock (divide by 4 i.e s_clk ) to our modem.

but we have not faced any issues regarding Transmit and receive. Modem Tx spectrum is clean and gives less than 1 % EVM.

even modem locks and we cam able to run end to end throughput also.

only issues we are facing is Input sampling rate goes down to '0' sometimes.

Do you understand my concerns from above?
With no fifo, data is presented on 4 x clk and sampled on clk. You have not said anything about handling this? Doesn't your design get timing violation?

Andrei