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Bitgen Error when changed sampling clock source (l_clk) from axi_ad9361_0 to axi_ad9361_1 in ZC702+FMCOMMS5 hdl_2019_r1 Ref Design

Category: Software
Product Number: AD9361,FMCOMMS5
Software Version: hdl_2019_r1 , no-os software

Hello ,

We are using FMCOMMS5+ZC706 Hardware platform for sat-com modem Development.

we have used chip B of FMCOMMS5 hardware i.e axi_ad9361_1 of the design for Transmit and Reception.

we can able to make use of the design but whenever hardware boots up it is not receiving sampling clock properly (we have wrote a VHDL code to report back the Sampling clock frequency received from AD9361 ).

bcz of this our modem is not Locking and we couldn't able to progress.

we tried changing the clock source form chip A to chip B but we are getting Bitgen Error as shown below.

BitGen Error vivado

Fig 1 : Bitgen error from vivado


Fig 2: axi_ad9361 we removed clock source


Fig 3: Alternative clock source for the design.

Final Design

Fig 4: Final Design

can anyone help me to solve this problem?

thank you.

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  • Thanks for the reply  

    I can able to generate bitstram by enabling use ssi clk in axi_ad9361 ip customisation.

    But still the problem Exists

    Sampling Clock (divided clk) from clk axi_clk_div is provided to modem for Modulation and demodulation shows 0 when read back.

    Can anyone suggest how to resolve it?

    By rebooting or reconfiguring ad9361 gives Clk rate properly .

    And Sometimes it shows 0.