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AD9208 Recommended for New Designs
The AD9208 is a dual, 14-bit, 3 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and- hold circuit designed for low...
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AD9208 on Analog.com

HMC7044 Recommended for New Designs
The HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise...
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HMC7044 on Analog.com

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AD9208 JESD Lane errors



		

			

									
					    Krishnapriya
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Feb 5, 2023 
				
			
			
		
    

				
		
    
		    		    
		    
		    		            		        
    Category: Hardware
    
    		        		        		    		    	
			
    Hello,
    

    We are using AD9208 on FMC board (HTG-FMC-14ADC-16DAC) connected to Kintex Ultrascale FPGA(HTG-KUS-PCIE-060-2) .
    

    We programmed the jesd link using these parameter values.
    

              M=2, L=8, N=16, F=1, S=2, Lane rate = 14.7456Gbps, Subclass = 1, ADC clock = 2.9GHz
    

    We are seeing some issues while debugging.
    

    1) After reading 0x7D register in HMC7044 (HMC7044 READ : Addr = 0X7D, Data = 0X1B), bit 2 indicates SYSREF of the HMC7044 is not valid; that is, its phase output is not stable. What does this mean?
    

    2) adxcvr reported some overflow/underflow errors. How can I fix this errors?
    

    ERR: ../src/axi_adxcvr.c:438:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL RX buffer underflow error, status: 0x61
    ERR: ../src/axi_adxcvr.c:445:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL RX buffer overflow error, status: 0x61
    

    3) I read the adi jesd IP status, it is in DATA status, but when I read the lane status, all lanes are still in INIT state. Also showing some jesd lane errors. Any ideas on what may be causing these issues?
    

     rx_0_jesd status:
    

     Link is enabled
     Measured Link Clock: 368.642 MHz
     Reported Link Clock: 368.640 MHz
     Lane rate: 14745.600 MHz
     Lane rate / 40: 368.640 MHz
     LMFC rate: 46.080 MHz
     Link status: DATA
     SYSREF captured: Yes
     SYSREF alignment error: No
    

     LANE 0 Status:
    JESD RX READ : Addr = 200, Data = 0 .
    Lane disable/enable register :0x0
    JESD RX READ : Addr = 280, Data = 3 .
    JESD RX READ : Addr = 300, Data = 10 .
    rx_0_jesd lane 0 status:
    JESD RX READ : Addr = 308, Data = 13 .
    Errors: 19
    JESD RX READ : Addr = 300, Data = 10 .
     CGS state: INIT
     Initial Frame Synchronization: Yes
    JESD RX READ : Addr = 210, Data = 1f .
    JESD RX READ : Addr = 304, Data = 18 .
     Lane Latency: 0 Multi-frames and 24 Octets
     Initial Lane Alignment Sequence: No
    


    LANE 1 Status:
    JESD RX READ : Addr = 200, Data = 0 .
    Lane disable/enable register :0x0
    JESD RX READ : Addr = 280, Data = 3 .
    JESD RX READ : Addr = 320, Data = 10 .
    rx_0_jesd lane 1 status:
    JESD RX READ : Addr = 328, Data = 16 .
    Errors: 22
    JESD RX READ : Addr = 320, Data = 10 .
     CGS state: INIT
     Initial Frame Synchronization: Yes
    JESD RX READ : Addr = 210, Data = 1f .
    JESD RX READ : Addr = 324, Data = 98 .
     Lane Latency: 4 Multi-frames and 24 Octets
     Initial Lane Alignment Sequence: No
    


    LANE 2 Status:
    JESD RX READ : Addr = 200, Data = 0 .
    Lane disable/enable register :0x0
    JESD RX READ : Addr = 280, Data = 3 .
    JESD RX READ : Addr = 340, Data = 10 .
    rx_0_jesd lane 2 status:
    JESD RX READ : Addr = 348, Data = 15 .
    Errors: 21
    JESD RX READ : Addr = 340, Data = 10 .
     CGS state: INIT
     Initial Frame Synchronization: Yes
    JESD RX READ : Addr = 210, Data = 1f .
    JESD RX READ : Addr = 344, Data = 74 .
     Lane Latency: 3 Multi-frames and 20 Octets
     Initial Lane Alignment Sequence: No
    


    LANE 3 Status:
    JESD RX READ : Addr = 200, Data = 0 .
    Lane disable/enable register :0x0
    JESD RX READ : Addr = 280, Data = 3 .
    JESD RX READ : Addr = 360, Data = 10 .
    rx_0_jesd lane 3 status:
    JESD RX READ : Addr = 368, Data = 15 .
    Errors: 21
    JESD RX READ : Addr = 360, Data = 10 .
     CGS state: INIT
     Initial Frame Synchronization: Yes
    JESD RX READ : Addr = 210, Data = 1f .
    JESD RX READ : Addr = 364, Data = 98 .
     Lane Latency: 4 Multi-frames and 24 Octets
     Initial Lane Alignment Sequence: No
    


    LANE 4 Status:
    JESD RX READ : Addr = 200, Data = 0 .
    Lane disable/enable register :0x0
    JESD RX READ : Addr = 280, Data = 3 .
    JESD RX READ : Addr = 380, Data = 10 .
    rx_0_jesd lane 4 status:
    JESD RX READ : Addr = 388, Data = 1a .
    Errors: 26
    JESD RX READ : Addr = 380, Data = 10 .
     CGS state: INIT
     Initial Frame Synchronization: Yes
    JESD RX READ : Addr = 210, Data = 1f .
    JESD RX READ : Addr = 384, Data = 57 .
     Lane Latency: 2 Multi-frames and 23 Octets
     Initial Lane Alignment Sequence: No
    


    LANE 5 Status:
    JESD RX READ : Addr = 200, Data = 0 .
    Lane disable/enable register :0x0
    JESD RX READ : Addr = 280, Data = 3 .
    JESD RX READ : Addr = 3a0, Data = 10 .
    rx_0_jesd lane 5 status:
    JESD RX READ : Addr = 3a8, Data = 22 .
    Errors: 34
    JESD RX READ : Addr = 3a0, Data = 10 .
     CGS state: INIT
     Initial Frame Synchronization: Yes
    JESD RX READ : Addr = 210, Data = 1f .
    JESD RX READ : Addr = 3a4, Data = b0 .
     Lane Latency: 5 Multi-frames and 16 Octets
     Initial Lane Alignment Sequence: No
    


    LANE 6 Status:
    JESD RX READ : Addr = 200, Data = 0 .
    Lane disable/enable register :0x0
    JESD RX READ : Addr = 280, Data = 3 .
    JESD RX READ : Addr = 3c0, Data = 10 .
    rx_0_jesd lane 6 status:
    JESD RX READ : Addr = 3c8, Data = 21 .
    Errors: 33
    JESD RX READ : Addr = 3c0, Data = 10 .
     CGS state: INIT
     Initial Frame Synchronization: Yes
    JESD RX READ : Addr = 210, Data = 1f .
    JESD RX READ : Addr = 3c4, Data = ac .
     Lane Latency: 5 Multi-frames and 12 Octets
     Initial Lane Alignment Sequence: No
    


    LANE 7 Status:
    JESD RX READ : Addr = 200, Data = 0 .
    Lane disable/enable register :0x0
    JESD RX READ : Addr = 280, Data = 3 .
    JESD RX READ : Addr = 3e0, Data = 10 .
    rx_0_jesd lane 7 status:
    JESD RX READ : Addr = 3e8, Data = 19 .
    Errors: 25
    JESD RX READ : Addr = 3e0, Data = 10 .
     CGS state: INIT
     Initial Frame Synchronization: Yes
    JESD RX READ : Addr = 210, Data = 1f .
    JESD RX READ : Addr = 3e4, Data = 44 .
     Lane Latency: 2 Multi-frames and 4 Octets
     Initial Lane Alignment Sequence: No     
    

    

    The detailed register programming sequences are given below.
    


    Please help us to debug.
    

    Thanks,
    

    Krishnapriya
    

    



    
    
    
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        reg_config.txt
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    HMC7044 WRITE : Addr = 0X0, Data = 0X1 .
HMC7044 WRITE : Addr = 0X0, Data = 0X0 .
HMC7044 WRITE : Addr = 0X46, Data = 0X0 .
HMC7044 WRITE : Addr = 0X47, Data = 0X0 .
HMC7044 WRITE : Addr = 0X48, Data = 0X0 .
HMC7044 WRITE : Addr = 0X49, Data = 0X0 .
HMC7044 WRITE : Addr = 0XC8, Data = 0X0 .
HMC7044 WRITE : Addr = 0XD2, Data = 0X0 .
HMC7044 WRITE : Addr = 0XDC, Data = 0X0 .
HMC7044 WRITE : Addr = 0XE6, Data = 0X0 .
HMC7044 WRITE : Addr = 0XF0, Data = 0X0 .
HMC7044 WRITE : Addr = 0XFA, Data = 0X0 .
HMC7044 WRITE : Addr = 0X104, Data = 0X0 .
HMC7044 WRITE : Addr = 0X10E, Data = 0X0 .
HMC7044 WRITE : Addr = 0X118, Data = 0X0 .
HMC7044 WRITE : Addr = 0X122, Data = 0X0 .
HMC7044 WRITE : Addr = 0X12C, Data = 0X0 .
HMC7044 WRITE : Addr = 0X136, Data = 0X0 .
HMC7044 WRITE : Addr = 0X140, Data = 0X0 .
HMC7044 WRITE : Addr = 0X14A, Data = 0X0 .
HMC7044 WRITE : Addr = 0X9F, Data = 0X4D .
HMC7044 WRITE : Addr = 0XA0, Data = 0XDF .
HMC7044 WRITE : Addr = 0XA5, Data = 0X6 .
HMC7044 WRITE : Addr = 0XA8, Data = 0X6 .
HMC7044 WRITE : Addr = 0XB0, Data = 0X4 .
HMC7044 WRITE : Addr = 0X5, Data = 0X2 .
HMC7044 WRITE : Addr = 0X3, Data = 0X2F .
HMC7044 READ : Addr = 0X3, Data = 0X2F .
HMC7044 WRITE : Addr = 0X33, Data = 0X1 .
HMC7044 WRITE : Addr = 0X34, Data = 0X0 .
HMC7044 WRITE : Addr = 0X35, Data = 0XC .
HMC7044 WRITE : Addr = 0X36, Data = 0X0 .
HMC7044 WRITE : Addr = 0X32, Data = 0X0 .
HMC7044 WRITE : Addr = 0X28, Data = 0X14 .
HMC7044 WRITE : Addr = 0X1C, Data = 0X1 .
HMC7044 WRITE : Addr = 0X1D, Data = 0X2 .
HMC7044 WRITE : Addr = 0X1E, Data = 0X1 .
HMC7044 WRITE : Addr = 0X1F, Data = 0X1 .
HMC7044 WRITE : Addr = 0X20, Data = 0X2 .
HMC7044 WRITE : Addr = 0X21, Data = 0X8 .
HMC7044 WRITE : Addr = 0X22, Data = 0X0 .
HMC7044 WRITE : Addr = 0X26, Data = 0X10 .
HMC7044 WRITE : Addr = 0X27, Data = 0X0 .
HMC7044 WRITE : Addr = 0X14, Data = 0X55 .
HMC7044 WRITE : Addr = 0X5C, Data = 0X0 .
HMC7044 WRITE : Addr = 0X5D, Data = 0X4 .
HMC7044 WRITE : Addr = 0X5A, Data = 0X7 .
HMC7044 WRITE : Addr = 0XA, Data = 0X0 .
HMC7044 WRITE : Addr = 0XB, Data = 0X7 .
HMC7044 WRITE : Addr = 0XC, Data = 0X0 .
HMC7044 WRITE : Addr = 0XD, Data = 0X0 .
HMC7044 WRITE : Addr = 0XE, Data = 0X5 .
HMC7044 WRITE : Addr = 0X46, Data = 0X0 .
HMC7044 WRITE : Addr = 0X47, Data = 0X0 .
HMC7044 WRITE : Addr = 0X48, Data = 0X0 .
HMC7044 WRITE : Addr = 0X49, Data = 0X0 .
HMC7044 WRITE : Addr = 0X50, Data = 0X1F .
HMC7044 WRITE : Addr = 0X51, Data = 0X2B .
HMC7044 WRITE : Addr = 0X52, Data = 0X0 .
HMC7044 WRITE : Addr = 0X53, Data = 0X0 .
HMC7044 WRITE : Addr = 0X12D, Data = 0X1 .
HMC7044 WRITE : Addr = 0X12E, Data = 0X0 .
HMC7044 WRITE : Addr = 0X134, Data = 0X8 .
HMC7044 WRITE : Addr = 0X12F, Data = 0X0 .
HMC7044 WRITE : Addr = 0X130, Data = 0X0 .
HMC7044 WRITE : Addr = 0X133, Data = 0X0 .
HMC7044 WRITE : Addr = 0X12C, Data = 0XC1 .
HMC7044 WRITE : Addr = 0X137, Data = 0X0 .
HMC7044 WRITE : Addr = 0X138, Data = 0X2 .
HMC7044 WRITE : Addr = 0X13E, Data = 0X8 .
HMC7044 WRITE : Addr = 0X139, Data = 0X0 .
HMC7044 WRITE : Addr = 0X13A, Data = 0X0 .
HMC7044 WRITE : Addr = 0X13D, Data = 0X0 .
HMC7044 WRITE : Addr = 0X136, Data = 0X4D .
HMC7044 WRITE : Addr = 0X105, Data = 0X4 .
HMC7044 WRITE : Addr = 0X106, Data = 0X0 .
HMC7044 WRITE : Addr = 0X10C, Data = 0X10 .
HMC7044 WRITE : Addr = 0X107, Data = 0X0 .
HMC7044 WRITE : Addr = 0X108, Data = 0X0 .
HMC7044 WRITE : Addr = 0X10B, Data = 0X0 .
HMC7044 WRITE : Addr = 0X104, Data = 0XC1 .
HMC7044 WRITE : Addr = 0XF1, Data = 0X8 .
HMC7044 WRITE : Addr = 0XF2, Data = 0X0 .
HMC7044 WRITE : Addr = 0XF8, Data = 0X10 .
HMC7044 WRITE : Addr = 0XF3, Data = 0X0 .
HMC7044 WRITE : Addr = 0XF4, Data = 0X0 .
HMC7044 WRITE : Addr = 0XF7, Data = 0X0 .
HMC7044 WRITE : Addr = 0XF0, Data = 0XC1 .
HMC7044 WRITE : Addr = 0X10F, Data = 0X0 .
HMC7044 WRITE : Addr = 0X110, Data = 0X2 .
HMC7044 WRITE : Addr = 0X116, Data = 0X10 .
HMC7044 WRITE : Addr = 0X111, Data = 0X0 .
HMC7044 WRITE : Addr = 0X112, Data = 0X0 .
HMC7044 WRITE : Addr = 0X115, Data = 0X0 .
HMC7044 WRITE : Addr = 0X10E, Data = 0X4D .
HMC7044 WRITE : Addr = 0XFB, Data = 0X0 .
HMC7044 WRITE : Addr = 0XFC, Data = 0X2 .
HMC7044 WRITE : Addr = 0X102, Data = 0X10 .
HMC7044 WRITE : Addr = 0XFD, Data = 0X0 .
HMC7044 WRITE : Addr = 0XFE, Data = 0X0 .
HMC7044 WRITE : Addr = 0X101, Data = 0X0 .
HMC7044 WRITE : Addr = 0XFA, Data = 0X4D .
HMC7044 WRITE : Addr = 0X1, Data = 0X2 .
HMC7044 WRITE : Addr = 0X1, Data = 0X0 .
HMC7044 WRITE : Addr = 0X1, Data = 0X8 .
HMC7044 WRITE : Addr = 0X1, Data = 0X4 .
HMC7044 WRITE : Addr = 0X1, Data = 0X0 .
HMC7044 READ : Addr = 0X7D, Data = 0X1B .

AD9208 READ : Addr = 0X11B, Data = 0X1 .
AD9208 WRITE : Addr = 0X0, Data = 0X0 .
AD9208 WRITE : Addr = 0X1, Data = 0X80 .
AD9208 WRITE : Addr = 0XA, Data = 0XFB .
AD9208 WRITE : Addr = 0X0, Data = 0X81 .
AD9208 WRITE : Addr = 0X1, Data = 0X82 .
AD9208 READ : Addr = 0X591, Data = 0X21 .
AD9208 READ : Addr = 0X592, Data = 0X80 .
AD9208 READ : Addr = 0X3, Data = 0X3 .
AD9208 READ : Addr = 0X5, Data = 0X0 .
AD9208 READ : Addr = 0X4, Data = 0XDF .
AD9208 READ : Addr = 0X6, Data = 0X3 .
AD9208 WRITE : Addr = 0X8, Data = 0X3 .
AD9208 WRITE : Addr = 0X3F, Data = 0X80 .
AD9208 WRITE : Addr = 0X11C, Data = 0X1 .
AD9208 WRITE : Addr = 0X11E, Data = 0X1 .
AD9208 READ : Addr = 0X108, Data = 0X0 .
AD9208 WRITE : Addr = 0X108, Data = 0X0 .
AD9208 WRITE : Addr = 0X1908, Data = 0X0 .
AD9208 READ : Addr = 0X18E3, Data = 0X0 .
AD9208 WRITE : Addr = 0X18E3, Data = 0X0 .
AD9208 WRITE : Addr = 0X18A6, Data = 0X0 .
AD9208 WRITE : Addr = 0X1910, Data = 0XD .
AD9208 WRITE : Addr = 0X1A4C, Data = 0X1E .
AD9208 WRITE : Addr = 0X1A4D, Data = 0X1E .
AD9208 READ : Addr = 0X18E3, Data = 0X0 .
AD9208 WRITE : Addr = 0X18E3, Data = 0X1E .
AD9208 READ : Addr = 0X11B, Data = 0X1 .
AD9208 READ : Addr = 0X200, Data = 0X0 .
AD9208 WRITE : Addr = 0X200, Data = 0X0 .
AD9208 READ : Addr = 0X201, Data = 0X0 .
AD9208 WRITE : Addr = 0X201, Data = 0X0 .
AD9208 WRITE : Addr = 0X8, Data = 0X1 .
AD9208 WRITE : Addr = 0X550, Data = 0X0 .
AD9208 WRITE : Addr = 0X8, Data = 0X3 .
AD9208 WRITE : Addr = 0X8, Data = 0X2 .
AD9208 WRITE : Addr = 0X550, Data = 0X0 .
AD9208 WRITE : Addr = 0X8, Data = 0X3 .
AD9208 READ : Addr = 0X578, Data = 0X0 .
AD9208 WRITE : Addr = 0X578, Data = 0X0 .
AD9208 READ : Addr = 0X120, Data = 0X0 .
AD9208 WRITE : Addr = 0X120, Data = 0X0 .
AD9208 WRITE : Addr = 0X122, Data = 0X0 .
AD9208 READ : Addr = 0X120, Data = 0X0 .
AD9208 WRITE : Addr = 0X120, Data = 0X2 .
AD9208 READ : Addr = 0X121, Data = 0X0 .
AD9208 WRITE : Addr = 0X121, Data = 0XF .
AD9208 READ : Addr = 0X201, Data = 0X0 .
AD9208 READ : Addr = 0X56E, Data = 0X30 .
AD9208 WRITE : Addr = 0X56E, Data = 0X30 .
AD9208 WRITE : Addr = 0X58E, Data = 0X1 .
AD9208 WRITE : Addr = 0X58F, Data = 0XF .
AD9208 READ : Addr = 0X590, Data = 0X2F .
AD9208 WRITE : Addr = 0X590, Data = 0X2F .
AD9208 WRITE : Addr = 0X58C, Data = 0X0 .
AD9208 WRITE : Addr = 0X58D, Data = 0X1F .
AD9208 READ : Addr = 0X58B, Data = 0X87 .
AD9208 WRITE : Addr = 0X58B, Data = 0X87 .
AD9208 READ : Addr = 0X590, Data = 0X2F .
AD9208 WRITE : Addr = 0X590, Data = 0X2F .
AD9208 READ : Addr = 0X58B, Data = 0X87 .
AD9208 WRITE : Addr = 0X58B, Data = 0X87 .
AD9208 READ : Addr = 0X571, Data = 0X14 .
AD9208 WRITE : Addr = 0X1228, Data = 0X4F .
AD9208 WRITE : Addr = 0X1228, Data = 0XF .
AD9208 WRITE : Addr = 0X1222, Data = 0X0 .
AD9208 WRITE : Addr = 0X1222, Data = 0X4 .
AD9208 WRITE : Addr = 0X1222, Data = 0X0 .
AD9208 WRITE : Addr = 0X1262, Data = 0X8 .
AD9208 WRITE : Addr = 0X1262, Data = 0X0 .
AD9208 WRITE : Addr = 0X571, Data = 0X14 .
AD9208 WRITE : Addr = 0X572, Data = 0X10 .
AD9208 READ : Addr = 0X571, Data = 0X14 .
AD9208 READ : Addr = 0X572, Data = 0X10 .
AD9208 READ : Addr = 0X573, Data = 0X0 .
AD9208 READ : Addr = 0X574, Data = 0X0 .
AD9208 READ : Addr = 0X591, Data = 0X21 .
AD9208 READ : Addr = 0X592, Data = 0X80 .
AD9208 READ : Addr = 0X56F, Data = 0X88 .
AD9208 PLL LOCKED
AD9208 READ : Addr = 0X2, Data = 0X0 .
AD9208 successfully initialized
HMC7044 Init and AD9208 Init completed. Press <Enter> to continue...

ADXCVR READ : Addr = 24, Data = 151008 .
ADXCVR READ : Addr = 0, Data = 110561 .
ADXCVR READ : Addr = 1C, Data = 2021403 .
ADXCVR READ : Addr = 140, Data = 3B6 .
ADXCVR WRITE : Addr = 10, Data = 0 .
ADXCVR WRITE : Addr = 20, Data = 1033 .
ADXCVR WRITE : Addr = 40, Data = 0 .
ADXCVR WRITE : Addr = 44, Data = 140000 .
ADXCVR READ : Addr = 48, Data = 12 .
ADXCVR WRITE : Addr = 40, Data = 0 .
ADXCVR WRITE : Addr = 44, Data = 10140012 .
ADXCVR READ : Addr = 48, Data = 12 .
ADXCVR WRITE : Addr = 40, Data = 0 .
ADXCVR WRITE : Addr = 44, Data = 140000 .
ADXCVR READ : Addr = 48, Data = 12 .
ADXCVR WRITE : Addr = 40, Data = 0 .
ADXCVR WRITE : Addr = 44, Data = 180000 .
ADXCVR READ : Addr = 48, Data = 830 .
ADXCVR WRITE : Addr = 40, Data = 0 .
ADXCVR WRITE : Addr = 44, Data = 10180830 .
ADXCVR READ : Addr = 48, Data = 830 .
ADXCVR WRITE : Addr = 40, Data = 0 .
ADXCVR WRITE : Addr = 44, Data = 180000 .
ADXCVR READ : Addr = 48, Data = 830 .
ADXCVR WRITE : Addr = 60, Data = 0 .
ADXCVR WRITE : Addr = 64, Data = 630000 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 0 .
ADXCVR WRITE : Addr = 64, Data = 106380c0 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 0 .
ADXCVR WRITE : Addr = 64, Data = 630000 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 0 .
ADXCVR WRITE : Addr = 64, Data = 6d0000 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 0 .
ADXCVR WRITE : Addr = 64, Data = 106d00e8 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 0 .
ADXCVR WRITE : Addr = 64, Data = 6d0000 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 1 .
ADXCVR WRITE : Addr = 64, Data = 630000 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 1 .
ADXCVR WRITE : Addr = 64, Data = 106380c0 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 1 .
ADXCVR WRITE : Addr = 64, Data = 630000 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 1 .
ADXCVR WRITE : Addr = 64, Data = 6d0000 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 1 .
ADXCVR WRITE : Addr = 64, Data = 106d00e8 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 1 .
ADXCVR WRITE : Addr = 64, Data = 6d0000 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 2 .
ADXCVR WRITE : Addr = 64, Data = 630000 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 2 .
ADXCVR WRITE : Addr = 64, Data = 106380c0 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 2 .
ADXCVR WRITE : Addr = 64, Data = 630000 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 2 .
ADXCVR WRITE : Addr = 64, Data = 6d0000 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 2 .
ADXCVR WRITE : Addr = 64, Data = 106d00e8 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 2 .
ADXCVR WRITE : Addr = 64, Data = 6d0000 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 3 .
ADXCVR WRITE : Addr = 64, Data = 630000 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 3 .
ADXCVR WRITE : Addr = 64, Data = 106380c0 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 3 .
ADXCVR WRITE : Addr = 64, Data = 630000 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 3 .
ADXCVR WRITE : Addr = 64, Data = 6d0000 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 3 .
ADXCVR WRITE : Addr = 64, Data = 106d00e8 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 3 .
ADXCVR WRITE : Addr = 64, Data = 6d0000 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 40, Data = 4 .
ADXCVR WRITE : Addr = 44, Data = 140000 .
ADXCVR READ : Addr = 48, Data = 12 .
ADXCVR WRITE : Addr = 40, Data = 4 .
ADXCVR WRITE : Addr = 44, Data = 10140012 .
ADXCVR READ : Addr = 48, Data = 12 .
ADXCVR WRITE : Addr = 40, Data = 4 .
ADXCVR WRITE : Addr = 44, Data = 140000 .
ADXCVR READ : Addr = 48, Data = 12 .
ADXCVR WRITE : Addr = 40, Data = 4 .
ADXCVR WRITE : Addr = 44, Data = 180000 .
ADXCVR READ : Addr = 48, Data = 810 .
ADXCVR WRITE : Addr = 40, Data = 4 .
ADXCVR WRITE : Addr = 44, Data = 10180810 .
ADXCVR READ : Addr = 48, Data = 810 .
ADXCVR WRITE : Addr = 40, Data = 4 .
ADXCVR WRITE : Addr = 44, Data = 180000 .
ADXCVR READ : Addr = 48, Data = 810 .
ADXCVR WRITE : Addr = 60, Data = 4 .
ADXCVR WRITE : Addr = 64, Data = 630000 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 4 .
ADXCVR WRITE : Addr = 64, Data = 106380c0 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 4 .
ADXCVR WRITE : Addr = 64, Data = 630000 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 4 .
ADXCVR WRITE : Addr = 64, Data = 6d0000 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 4 .
ADXCVR WRITE : Addr = 64, Data = 106d00e8 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 4 .
ADXCVR WRITE : Addr = 64, Data = 6d0000 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 5 .
ADXCVR WRITE : Addr = 64, Data = 630000 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 5 .
ADXCVR WRITE : Addr = 64, Data = 106380c0 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 5 .
ADXCVR WRITE : Addr = 64, Data = 630000 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 5 .
ADXCVR WRITE : Addr = 64, Data = 6d0000 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 5 .
ADXCVR WRITE : Addr = 64, Data = 106d00e8 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 5 .
ADXCVR WRITE : Addr = 64, Data = 6d0000 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 6 .
ADXCVR WRITE : Addr = 64, Data = 630000 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 6 .
ADXCVR WRITE : Addr = 64, Data = 106380c0 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 6 .
ADXCVR WRITE : Addr = 64, Data = 630000 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 6 .
ADXCVR WRITE : Addr = 64, Data = 6d0000 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 6 .
ADXCVR WRITE : Addr = 64, Data = 106d00e8 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 6 .
ADXCVR WRITE : Addr = 64, Data = 6d0000 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 7 .
ADXCVR WRITE : Addr = 64, Data = 630000 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 7 .
ADXCVR WRITE : Addr = 64, Data = 106380c0 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 7 .
ADXCVR WRITE : Addr = 64, Data = 630000 .
ADXCVR READ : Addr = 68, Data = 80C0 .
ADXCVR WRITE : Addr = 60, Data = 7 .
ADXCVR WRITE : Addr = 64, Data = 6d0000 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 7 .
ADXCVR WRITE : Addr = 64, Data = 106d00e8 .
ADXCVR READ : Addr = 68, Data = E8 .
ADXCVR WRITE : Addr = 60, Data = 7 .
ADXCVR WRITE : Addr = 64, Data = 6d0000 .
ADXCVR READ : Addr = 68, Data = E8 .
adxcvr_init completed. Press <Enter> to continue...
ADXCVR WRITE : Addr = 10, Data = 0 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
rx_0_adxcvr: OK (14745600 kHz)
ADXCVR WRITE : Addr = 10, Data = 3 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
ADXCVR WRITE : Addr = 10, Data = 0 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
rx_0_adxcvr: OK (14745600 kHz)
ADXCVR WRITE : Addr = 10, Data = 3 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
ADXCVR WRITE : Addr = 10, Data = 0 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
rx_0_adxcvr: OK (14745600 kHz)
ADXCVR WRITE : Addr = 10, Data = 3 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
ADXCVR WRITE : Addr = 10, Data = 0 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
rx_0_adxcvr: OK (14745600 kHz)
ADXCVR WRITE : Addr = 10, Data = 3 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
ADXCVR WRITE : Addr = 10, Data = 0 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
rx_0_adxcvr: OK (14745600 kHz)
ADXCVR WRITE : Addr = 10, Data = 3 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
ADXCVR WRITE : Addr = 10, Data = 0 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
rx_0_adxcvr: OK (14745600 kHz)
ADXCVR WRITE : Addr = 10, Data = 3 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
ADXCVR WRITE : Addr = 10, Data = 0 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
rx_0_adxcvr: OK (14745600 kHz)
ADXCVR WRITE : Addr = 10, Data = 3 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
ADXCVR WRITE : Addr = 10, Data = 0 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
rx_0_adxcvr: OK (14745600 kHz)
ADXCVR WRITE : Addr = 10, Data = 3 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
ADXCVR WRITE : Addr = 10, Data = 0 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
rx_0_adxcvr: OK (14745600 kHz)
ADXCVR WRITE : Addr = 10, Data = 3 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
ADXCVR WRITE : Addr = 10, Data = 0 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
rx_0_adxcvr: OK (14745600 kHz)
ADXCVR WRITE : Addr = 10, Data = 3 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
ADXCVR WRITE : Addr = 10, Data = 0 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
rx_0_adxcvr: OK (14745600 kHz)
ADXCVR WRITE : Addr = 10, Data = 3 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
ADXCVR WRITE : Addr = 10, Data = 0 .
ADXCVR WRITE : Addr = 10, Data = 1 .
ADXCVR READ : Addr = 14, Data = 61 .
rx_0_adxcvr: OK (14745600 kHz)
ERR: ../src/axi_adxcvr.c:438:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL RX buffer underflow error, status: 0x61
ERR: ../src/axi_adxcvr.c:445:adxcvr_clk_enable(): adxcvr_clk_enable: QPLL RX buffer overflow error, status: 0x61
adxcvr_clk_enable completed. Press <Enter> to continue...
JESD RX READ : Addr = c, Data = 32303452 .
JESD RX READ : Addr = 0, Data = 10761 .
JESD RX READ : Addr = 10, Data = 8 .
JESD RX READ : Addr = 14, Data = 402 .
JESD RX READ : Addr = 18, Data = 11101 .
JESD RX WRITE : Addr = c0, Data = 1 .
JESD RX WRITE : Addr = 210, Data = 1f .
JESD RX WRITE : Addr = 21c, Data = 7 .
axi_jesd204_rx_init completed. Press <Enter> to continue...
JESD RX WRITE : Addr = 108, Data = 3 .
JESD RX WRITE : Addr = c0, Data = 0 .
axi_jesd204_rx_lane_clk_enable completed. Press <Enter> to continue...
AD9208 READ : Addr = 0X120, Data = 0X2 .
AD9208 READ : Addr = 0X121, Data = 0XF .
AD9208 READ : Addr = 0X122, Data = 0X0 .
AD9208 READ : Addr = 0X123, Data = 0X40 .
AD9208 READ : Addr = 0X128, Data = 0X80 .
AD9208 READ : Addr = 0X129, Data = 0X1 .
AD9208 READ : Addr = 0X12A, Data = 0X62 .
JESD RX READ : Addr = 300, Data = 10 .
JESD RX READ : Addr = 320, Data = 10 .
JESD RX READ : Addr = 340, Data = 10 .
JESD RX READ : Addr = 360, Data = 10 .
JESD RX READ : Addr = 380, Data = 10 .
JESD RX READ : Addr = 3a0, Data = 10 .
JESD RX READ : Addr = 3c0, Data = 10 .
JESD RX READ : Addr = 3e0, Data = 10 .
JESD RX READ : Addr = c4, Data = 0 .
JESD RX READ : Addr = 280, Data = 3 .
JESD RX READ : Addr = 108, Data = 1 .
JESD RX READ : Addr = c8, Data = 3afb9 .
JESD RX READ : Addr = 100, Data = 0 .
JESD RX READ : Addr = 210, Data = 1f .
rx_0_jesd status:
        Link is enabled
        Measured Link Clock: 368.642 MHz
        Reported Link Clock: 368.640 MHz
        Lane rate: 14745.600 MHz
        Lane rate / 40: 368.640 MHz
        LMFC rate: 46.080 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
axi_jesd204_rx_status_read completed. Press <Enter> to continue...
AXI ADC WRITE : Addr = 40, Data = 0 .
AXI ADC WRITE : Addr = 40, Data = 3 .
AXI ADC WRITE : Addr = 400, Data = 51 .
AXI ADC WRITE : Addr = 440, Data = 51 .
AXI ADC READ : Addr = 5c, Data = 5 .
AXI ADC READ : Addr = 54, Data = 3afb9 .
AXI ADC READ : Addr = 58, Data = 8 .
rx_0_adc: Successfully initialized (2949133300 Hz)
axi_adc_init completed. Press <Enter> to continue...
AXI ADC READ : Addr = 5c, Data = 5 .
AXI ADC READ : Addr = 54, Data = 3afb9 .
AXI ADC READ : Addr = 58, Data = 8 .
rx_0_adc: Successfully initialized (2949133300 Hz)


    

    


    

    
										

    
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[edited by: Krishnapriya at 7:34 AM (GMT -5) on 6 Feb 2023]
				
    
					
    

				
				
		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    


	















    
	
    
	
    
					



			


				
	









	
      
	

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      •  Analog Employees  
      
            
			                            
                        
                on Feb 7, 2023 9:27 AM
            
            
					
      
	
      

		
		
      
					
      Hello,
      

      Have you used Xilinx FPGAs Transceivers Wizard [Analog Devices Wiki] to select the correct parameters for UTIL_ADXCVR ?
      

      Regards,
      

      Adrian
      
			
      

		
		
		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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													0
							
			
				
									
							        
			
			
			
        
            
			                            
                        
                on Feb 7, 2023 10:07 AM
            
            
												
						in reply to AdrianC
					
									
        
	
        

		
		
        
					
        Hi Adrian,
        

             Yes. 
        

        Thanks & Regards,
        

        Krishnapriya
        
			
        

		
		
		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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        •  Analog Employees  
        
            
			                            
                        
                on Feb 7, 2023 8:07 PM
            
            
												
						in reply to Krishnapriya
					
									
        
	
        

		
		
        
					
        Hello,
        

        1. For best answer to this question, please open a ticket on the (+) Clock and Timing - EngineerZone (analog.com) forum. 
        

        Regarding 2&3, I need to further investigate. Is your software based on the latest HDL & No-OS branch ? Or are you using your own custom HDL & software?
        

        Could you try using half the rate / half the sampling rate to understand if the issue is related to the lane speed ?
        

        Can you add an ILA to see how the link is established and where things go wrong ?
        

        Regards,
        

        Adrian
        
			
        

		
		
		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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                on Feb 8, 2023 7:34 AM
            
            
												
						in reply to AdrianC
					
									
          
	
          

		
		
          
					
          Hi Adrian,
          

          Thank you for the suggestion.
          

          We are using an edited version of the Reference design/software provided by ADI for Virtex Ultrascale design with Dual AD9208 FMC Board. The FMC board that we are using has only one AD9208.
          

          We tried reducing the sampling frequency from 2.94912 GHz to 2.58048 GHz, as per your suggestion. Now we were able to get lane status as data and we are able to capture ramp test waveforms as well as analog input waveforms! 
          

          However, we are having some issues with the samples received.
          

          In case of ramp output (ADC0 TEST MODE), we see that the we are receiving samples which are multiples of 4 (Vs increment of 1). We are also seeing a periodic jump by 36 counts. Below is an example of what we are getting:
          


          156
          160
          164
          168
          172
          208  <--- Jump of 36
          212
          216
          220
          224
          228
          232
          236
          272 <--- Jump by 36
          276
          280
          284
          288
          292
          296
          300
          

           
          

          

          In the case of analog samples (ADC1 input waveform of 10 MHz, Amplitude 1.5V, sampling rate: 2.58048 GHz), we are seeing that a decimation by 2 is happening although DDC is disabled. We also see a significant skip of samples similar to the ramp waveform. Please see below samples attached.
          

           
          

          As you can see above, we are getting approximately 128 samples per wavelet, while it should have been 256 samples .  We are also seeing some non-uniformity in the waveform (periodic jumps). 
          

          Could you please shed some light into why this could be happening. 
          

          We are also trying to understand how the reduction in Sampling frequency helped in achieving JESD Lane DATA state.
          

          

          Thanks & Regards,
          

          Krishnapriya.
          
			
          

		
		
		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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          •  Analog Employees  
          
            
			                            
                        
                on Feb 9, 2023 4:49 PM
            
            
												
						in reply to Krishnapriya
					
									
          
	
          

		
		
          
					
          Hello Krishnapriya,
          

          Can you DMA keep up with the sampling rate ? Is it correctly configured for your design ? Are you using a similar ADC FIFO in your design ? Is the TPL correctly configured ?
          

          If you put an ILA in the datapath, do you see the missing samples ?
          

          Regarding the reduced sampling frequency, it's possible that either the eval board or the carrier you are using is not validated to the maximum rates so the problem to be physical? 
          

          Regards,
          

          Adrian
          
			
          

		
		
		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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													+1
							
			
				
									
							        
			
			
			
            
            
			                            
                        
                on Feb 9, 2023 6:04 PM
            
            
												
						in reply to AdrianC
					
									
            
	
            

		
		
            
					
            Hi Adrian,
             
             Thanks.
             
             We are using XILINX ASYNC FIFO with sufficient depth and are DMA-ing only a small number of samples (4096) from this FIFO.  Once the FIFO gets filled-up in the beginning, it will not take any more samples from the TPL core until we DMA out those samples. So we are not expecting any sample-loss due to DMA.  
             
             Unfortunately XILINX ILA doesn't work for non-free running clocks. The data at the input side of FIFO which is the output of the TPL Core is clocked using the global-clock from FMC board which is not free running (available only after initializing the HMC7044). So we can't see these samples, we can see only the output side of the FIFO, which runs at DMA clock.
             
             Regarding TPL Core configuration, we are using the following parameters.  Do you have any specific parameter in mind that can cause such periodic sample loss ?
             
              
             
            BTW, we tried using the JESD interface TEST RAMP pattern by programming 0x0573 register and we are getting RAMP data received without loss of numbers, but every number in the RAMP pattern repeated twice.  Not sure if this can shed any light into the issue.
            

            We would also like to add a common observation between RAMP and ANALOG INPUT samples. In both cases we see that, we are loosing 8 samples for every 8 samples received.  We now realize that the reduced sample rate (by half) was actually due to this loss of samples. Could this be because some inconsistency in JESD parameter settings?
             
             Thanks again for your help with this! 
             
             Regards
             Krishnapriya
            
			
            

		
		
		
		
	
            
	
            
		
            
			
		
            
	
            
	
            
		
						
				
						
						
				
				
		
		
            
			
		
            
	
            

            

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                on Feb 20, 2023 7:57 AM
            
            
												
						in reply to Krishnapriya
					
									
              
	
              

		
		
              
					
              Thanks for the help Adrian,
              

                    We are able to successfully capture the samples from ADC now. The issue was with DMA.
              

              Regards,
              

              Krishnapriya
              
			
              

		
		
		
		
	
              
	
              
		
              
			
		
              
	
              
	
              
		
						
						
				
						
				
				
		
		
              
			
		
              
	
              

              

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              •  Analog Employees  
              
            
			                            
                        
                on Feb 20, 2023 8:24 AM
            
            
												
						in reply to Krishnapriya
					
									
              
	
              

		
		
              
					
              Hello Krishnapriya,
              

              

              Good to hear you found a solution.
              

              

              Could you add additional details regarding the issue, for future reference?
              

              

              Regards,
              

              Adria
              
			
              

		
		
		
		
	
              
	
              
		
              
			
		
              
	
              
	
              
		
						
						
				
						
				
				
		
		
              
			
		
              
	
              

              

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                on Feb 20, 2023 2:14 PM
            
            
												
						in reply to AdrianC
					
									
                
	
                

		
		
                
					
                Hi Adrian,
                

                We are using our custom DMA which we had never tested out for 128 bit / 256 bit. Now we fixed the bug and updated the data width parameter. It worked.
                

                Regards,
                

                Krishnapriya
                
			
                

		
		
		
		
	
                
	
                
		
                
			
		
                
	
                
	
                
		
						
						
				
						
				
				
		
		
                
			
		
                
	
                

                

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