Facing issue in Cygwin while recreating vivado ip design

Hello,

I would recommend you to make yourself familiar with our flow of building projects (since you're trying to build one of our projects) https://wiki.analog.com/resources/fpga/docs/build 

Also, as I stated in this thread  adc9467_fmc_ebz.c generates issues with APIs (which I think that user goes by the same guide as you since the uploaded picture is exactly the same as that one from your guide from the Xilinx support forum) we don't support anymore such old tools (Vivado 2018) and old release branches (from before 2019). 

Best regards,
Iulia