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adc9467_fmc_ebz.c generates issues with APIs

Category: Hardware
Product Number: ADC9467 Eval Board

We are using the following hardware:

  1. ADC9467 Eval board:
  2. Software: Xilinx SDK 2018.2
  3. Version: NO_OS (2018_R1) 

Here is the hardware block design we generated using Vivado 2018.2

Plz verify the block design if there are any issues with it.

We exported the design to software and are trying to run the full test (ad9467_fmc_ebz.c)

This is what we are expecting to achieve the full test functionality.

Here are the issues. As soon as we define Zynq as our platform, all the parameters liek XSPIPS_CR_OFFSET, XSPIPS_CR_SSCTRL_MASK etc are undefined. 

Why is the software broken when we are using all the files from the same link https://github.com/analogdevicesinc/no-OS/tree/2018_R1/ad9467-fmc-ebz

Until we can find the answer to SPI read/ write functions working properly, we cannot proceed with the test successfully.

Plz help ASAP

  • Hello,

    Since this is a very very old release, we don't have this version of tools anymore so we can't test it. Can't you use a newer release?

    Also, do you use Zedboard as carrier?

    Did you do any edits to the provided HDL and No-OS code?

    Regards,
    Iulia

  • Thanks for the reply. It will be better if you suggest us a newer release version for Vivado 2018.2 which has no compatibility issues at all. 

    Yes, we are using Xilinx Zynq®-7000 SoC as a carrier to configure and initiate the ADC (ad9467 chip and ad9517 clock chip) in order to change the frequency of the clock chip using SDK 2018.2.



    Yes, we exactly use the provided HDL and No-OS code from  https://github.com/analogdevicesinc/no-OS/tree/2018_R1/ad9467-fmc-ebz

    It will be fine if you recommend which HDL and No-OS is compatible with Vivado 2018.2. 

  • By using a newer release, I meant both changing the branch from GitHub and using Vivado/SDK 2019.1 at least.

    Vivado/SDK 2019.1 is the oldest version that we support at the moment. Soon this will be deprecated too.

    Check our Releases page and choose which you deem fit to use, but we recommend from hdl_2019_r2 onwards.

    Best regards,
    Iulia

  • Now, we will try to use the release version hdl_2019_r2 in Vivado / SDK 2019.1. 

    Is hdl_2018_r2 is useless at a moment?

  • We are using the following hardware:

    1. ADC9467 Eval board:
    2. Software: Xilinx SDK 2018.2
    3. Version: NO_OS (2018_R2) 

    We take input from discovery 2 waveforms software setup shown below


    SDK Terminal shows below response

    *****************************************************

    *****************************************************


    ADI AD9467-FMC-EBZ Reference Design


    AD9467 CHIP ID: 0x50


    AD9467 CHIP GRADE: 0x20


    AD9517 CHIP ID: 0x4d3d3d3


    *****************************************************

    adc_setup adc core initialized (1 MHz).
    AD9467[0x016]: 00

    adc_delay: setting zero error delay (5)

    Error field (0=success, 1=fail):
    00000000000011111111111111111111
    ADC Test: mode - MIDSCALE


    format - OFFSET BINARY


    Test passed


    ADC Test: mode - MIDSCALE


    format - TWOS_COMPLEMENT


    ERROR[ 0]: rcv(80008000), exp(00000000)


    ERROR[ 1]: rcv(80008000), exp(00000000)

    ERROR[ 2]: rcv(80008000), exp(00000000)


    ERROR[ 3]: rcv(80008000), exp(00000000)


    ERROR[ 4]: rcv(80008000), exp(00000000)


    ERROR[ 5]: rcv(80008000), exp(00000000)

    ERROR[ 6]: rcv(80008000), exp(00000000)


    ERROR[ 7]: rcv(80008000), exp(00000000)

    ERROR[ 8]: rcv(80008000), exp(00000000)


    ERROR[ 9]: rcv(80008000), exp(00000000)


    ERROR[10]: rcv(80008000), exp(00000000)


    ERROR[11]: rcv(80008000), exp(00000000)

    ERROR[12]: rcv(80008000), exp(00000000)

    ERROR[13]: rcv(80008000), exp(00000000)

    ERROR[14]: rcv(80008000), exp(00000000)

    ERROR[15]: rcv(80008000), exp(00000000)

    ERROR[16]: rcv(80008000), exp(00000000)

    ERROR[17]: rcv(80008000), exp(00000000)


    ERROR[18]: rcv(80008000), exp(00000000)


    ERROR[19]: rcv(80008000), exp(00000000)


    ERROR[20]: rcv(80008000), exp(00000000)

    ERROR[21]: rcv(80008000), exp(00000000)


    ERROR[22]: rcv(80008000), exp(00000000)


    ERROR[23]: rcv(80008000), exp(00000000)


    ERROR[24]: rcv(80008000), exp(00000000)


    ERROR[25]: rcv(80008000), exp(00000000)

    ERROR[26]: rcv(80008000), exp(00000000)


    ERROR[27]: rcv(80008000), exp(00000000)


    ERROR[28]: rcv(80008000), exp(00000000)


    ERROR[29]: rcv(80008000), exp(00000000)


    ERROR[30]: rcv(80008000), exp(00000000)


    ERROR[31]: rcv(80008000), exp(00000000)

    Testing done.

    Start capturing data...

    Done.

    -----------------------------------------------------

    We successfully generated bitstream from the hdl_2018_R2 from https://github.com/analogdevicesinc/hdl/tree/hdl_2018_r2. 

    Kindly inform tell us about the Error shown in the SDK terminal.

    Plz help ASAP

  • Is hdl_2018_r2 is useless at a moment?

    Yes.

  • Hopefully, when I installed Vivado/SDK 2019.1 with the release version hdl_2019_r2 just gives me a green signal to run HDL_2019_r2 in Vivado 2019.1 then I will let you know about my problems if appears. Thanks for your cooperation.