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Minimum Frequency offset for Dual tone CW generation in AD9174

Category: Software
Product Number: AD9174
Software Version: Xilinx SDK 2019.1


I have a requirement to generate dual tone output from AD9174.For that I am using TPL_DAC_DDS(Internal DDS in Transport layer).

I am able to generate 2 tones with an offset of 1MHz(Ex: 100 MHz & 101 MHz) which can be clearly observed in Spectrum Analyzer, However I am not able to get 2 tones with an offset range between 5 to 20 kHz (Ex: 100 MHz & 100.005/100.020 MHz) which is my requirement. I am trying to program them along with the required offset but unable to distinguish them(as I was able to do for 1M offset) when observed in Spectrum Analyzer. I tried reducing the span but never got 2 peaks.

Is there any such minimum frequency offset that the TPL_DAC_DDS takes to generate 2 tones of different frequencies, or its the chip(AD9174) that has some limitations related to this?

I am using AD HDL for AD9174. Mode 8,Dual Link, Ref_clk = 250 MHz, DAC Input Clock = 3GHz,Interpolation = 12, Fout = 1G.I have attached a snap of the part of the code I am executing to generate dual tone using dds.(This snippet is from axi_dac_core.c)

Can I generate dual tone using DAC Internal NCO? or is it necessary to use DDS to do that.



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