I am using AD9174 DAC.I am trying to validate the entire data flow path from FPGA to AD9174, and observe the output signal using spectrum analyzer. I am trying to produce 1 GHz sine wave from DDS which is present inside the TPL DAC(dac_jesd204_transport) IP. JESD link is established successfully.
From the DAC device point of view, I have followed the Start-Up Sequence mentioned in the datasheet of AD9174, and using that I am enabling both the Main Datapath, and paging to both links as per sequence(Dual link). I am using the software driver code(of AD917x) provided by AD and using axi_dac_dds_set_frequency function. I am setting the required frequency I want to generate using DDS. I am using all the 8 channels since I want to generate dual tone per core.
With the above setup,I am able to observe sine wave peak in the analyzer for DAC1 core(channel B), However I am not getting any peak for DAC0 core(channel A), but just noise.We checked the Physical to Logical Lanes Mapping & found that it is set to default. When we tried to swap the lanes(0->4,1->5,2->6,3->7,4->0,5->1,6->2,7->3), then we were able to observe sine wave peak in DAC0 (channel A),but now not in DAC1. I was suspecting if the first 4 Physical lanes(0 to 3) are working properly or not.
So we performed a few deterministic experiments, and found that all the Physical lanes were working properly.Next,I wanted to check the data coming out of fpga,and put chipscope(ILA) into the data lines coming out from Link,Transport,cpack & FIFO IP of the AD RTL JESD Datapath for DAC.The 256 bits data bus is segregated into 16 bits each for the debug core so that it would be easy to debug & also to find out the I & Q data.I observed that there was data(sine wave) coming for pair of 16 bits & the corresponding pair of 16 bits was having some definitive pattern(may be a kind of sine wave) mixed with noise.
Also when I tried to read the tpl_dac channel register 0x400 to 0x5c0(since I have kept num_of_channels = 8 in software code), but I am getting read status(values) only for first 4 tpl_dac channels(0x400-0x4c0), & getting DEADEAD for 0x500 to 0x5co(which represents channel 4 to 8).I am not sure if the channels are disabled which is why I am not getting data on all the 256 bits.
In order to be sure if DDS is not working properly, we used axi_dac_load_custom_data (sine_lut_iq_array) function(provided in the AD driver code of AD917x), and feed it to DDR and through DMA tried to access that data and give it to DAC.We observed the same thing for this data too, so now we know that data is not coming out of fpga itself properly & since we have already got output on both the DAC channels(by swapping), so it seems the issue lies within the TPL IP core, & not with the chip.
I am not sure how the 256 bit data is concatenated or mapped to the xcvr(phy) layer and send out from FPGA.But I am able to get data for 128 bits & some noise for the remaining.Is the issue something to do with hdl branch repo or there might be any possible bug in the tpl_dac ip of this version.
Need some support & solution from the AD team on the same asap.
HDL Repo branch: hdl_2019_r1
JESD Mode:8(Dual link)
Main path Interpolation = 12 (Bypass Channel datapath)
Using DAC Internal NCO.
Input clock = 3Ghz (Using DAC PLL converting to 12 GHz)
Ref_clk = 250 Mhz
lane rate = 10Gbps
Using SDK 2019.1
I have attached a few snapshot of the data I have observed.Each data represented is 16 bits.
1. DDS data observation for TPL output
2. .DDR DMA sine lut iq array data observation for TPL output