ZCU102 & AD9174 boot couldn't reach opt_post_running_stage.

Question

Hi all, 
 I used following HW & SW setups and found that FSM state reached link_running and Linux boot sequence completed apparently successfully with neither moving on to opt_post_running_stage nor rolling back to previous state. Is this correct procedure? In my understanding, TXEN, etc. are not set in the boot sequence without reaching opt_post_running_stage since ad9172_finalize_setup() is not called. 
 . 
 
 ZCU102 & AD9174-FMC-EBZ as HW. 
 "$HDL_DIR/ projects\dac_fmc_ebz\zcu102/make" to create system_top.xsa (JESD mode 4 as default settings) 
 "./build_zynqmp_boot_bin.sh ./system_top.xsa ./u-boot.elf download" to create BOOT.bin. 
 "./build_zynqmp_kernel_image.sh ./linux-adi/ xilinx/zynqmp-zcu102-rev10-ad9172-fmc-ebz-mode4.dtb /opt/pkg/gcc-arm-8.3-2019.03-x86_64-aarch64-linux-gnu/bin/aarch64-linux-gnu-" to create Image and dtb. 
 Note: dtsi, dts, and $HDL_DIR/ projects\dac_fmc_ebz\common\ config.tcl are not changed from default.

mhennerich · Accepted Answer

Here we go - can you test ? 
 https://github.com/analogdevicesinc/linux/pull/2075 
 
 [ 4.899824] cf_axi_dds 84a04000.axi-ad9172-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x84A04000 mapped to 0x(____ptrval____), probed DDS AD917x [ 4.914684] axi_adxcvr 84a60000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.05.a) using QPLL on GTH4 at 0x84A60000. Number of lanes: 4. [ 4.926274] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition initialized -> probed [ 4.944244] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition probed -> idle [ 4.954329] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition idle -> device_init [ 4.964859] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition device_init -> link_init [ 4.981303] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_init -> link_supported [ 4.997133] hmc7044 spi1.0: hmc7044_jesd204_link_pre_setup: Link0 forcing continuous SYSREF mode [ 5.009062] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_supported -> link_pre_setup [ 5.032921] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1 [ 5.044663] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2 [ 5.056482] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3 [ 5.070329] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage3 -> link_setup [ 5.081714] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_setup -> opt_setup_stage1 [ 5.093188] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2 [ 5.105188] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3 [ 5.117182] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4 [ 5.129176] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5 [ 5.141181] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable [ 5.153332] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clocks_enable -> link_enable [ 5.175645] ad9172 spi1.1: Link0 code_grp_sync: f [ 5.180348] ad9172 spi1.1: Link0 frame_sync_stat: f [ 5.185217] ad9172 spi1.1: Link0 good_checksum_stat: f [ 5.190346] ad9172 spi1.1: Link0 init_lane_sync_stat: f [ 5.195562] ad9172 spi1.1: Link0 4 lanes @ 7372800 kBps [ 5.200785] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_enable -> link_running [ 5.212654] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_running -> opt_post_running_stage [ 5.224825] axi-jesd204-tx 84a90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0x84A90000. Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm. 
 -Michael)

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ZCU102 & AD9174 boot couldn't reach opt_post_running_stage.