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ZCU102 & AD9174 boot couldn't reach opt_post_running_stage.

Product Number: ZCU102, AD9174-FMC-EBZ

Hi all,

I used following HW & SW setups and found that FSM state reached link_running and Linux boot sequence completed apparently successfully with neither moving on to opt_post_running_stage nor rolling back to previous state. Is this correct procedure? In my understanding, TXEN, etc. are not set in the boot sequence without reaching opt_post_running_stage since ad9172_finalize_setup() is not called.

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ZCU102 & AD9174-FMC-EBZ as HW.

"$HDL_DIR/projects\dac_fmc_ebz\zcu102/make" to create system_top.xsa (JESD mode 4 as default settings)

"./build_zynqmp_boot_bin.sh ./system_top.xsa ./u-boot.elf download" to create BOOT.bin.

"./build_zynqmp_kernel_image.sh ./linux-adi/ xilinx/zynqmp-zcu102-rev10-ad9172-fmc-ebz-mode4.dtb /opt/pkg/gcc-arm-8.3-2019.03-x86_64-aarch64-linux-gnu/bin/aarch64-linux-gnu-" to create Image and dtb.

Note: dtsi, dts, and $HDL_DIR/projects\dac_fmc_ebz\common\config.tcl are not changed from default.

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  • Hello  ,

    I tried to boot this hardware with the default configuration(MODE 4) and on my side DAC0 of the the AD9174 works fine, but DAC1 doesn't output anything!

    This are the fails that I got on dmesg:

       

    Please let me know if you encountered the same problem and also send me the dmesg of your setup!

    Kind regards!

    Filip.

  • Hello Filip,

    Thanks for your reply. I also got the same dmesg as yours, but after the linux boot sequence, JESD link was successfully enabled and corresponding clock are set (confirmed with jesd_status command). I can also write/read some registers in AD9174, so I think JESD link and SPI themselves are OK.

    In $HDL_DIR/projects\dac_fmc_ebz\common\config.tcl, num_links is set to 1 (Single link) as default, so I think it is the expected behavior that DAC0 works (in my case, 40MHz tone is output) and DAC1 doesn't.

     

  • Moved to Linux Software Drivers for further support!

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