ADRV9361-z7035 FPGA Vivado Linux Toolchain General Question

LukeDy said:

Vivado/Xilinx have a real workflow that uses the GUI to incorporate a linux kernel (seems like maybe but at great effort)?

What do you mean here? The kernel is separate from the bitstreams.

LukeDy said:

Can I change the running FPGA image while the system is booted (seems like no)?

Yes. You can use something like fpga-manager https://www.kernel.org/doc/html/v4.19/driver-api/fpga/fpga-mgr.html

Note that if you reload the bitstream the drivers need to be rebound.

LukeDy said:

Am I wasting my time trying to find a GUI workpath, or am I avoiding learning about an important aspect of the Xilinx product by not doing so?

This is more of a preference at the end of the day. Now personally I have gravitated toward CLI tools since it enables scripting. There is usually something else I need to interact with besides Vivado or Vitis. Scripting allows for easy automation of standard tasks. For example, for your question above I could write a script to repackage the bitstream into a BOOT.BIN, copy it to the board, and reboot. Or SSH to the board load the bitstream with fpga-manager and rebind the drivers.

If you want to understand the tools better I would reach out to Xilinx.

-Travis

Hi Travis, thank you so much for your response. I have basically gotten to the point of modifying the FPGA image, rebuilding the SD card image, and then trying things. I can get python to talk to the IIO devices, but what I'd really like to do is touch specific registers in the axi memory space. 

For example, in the device tree I have a dma mapped to 7c42000, and I would like to add some additional registers to the verilog, rebuild and move data around/control behavior via software. Outside of IIO mapped tools in python, and some command line sysfs type manipulations of what is already there, how would I go about just poking individual addresses? Is it really a low-level C type thing I need to do, or does Python have a way somewhere in the guts?

I apologize for the loaded question, but it seems this comes up for everyone on here. I am fine doing C wrapped for python, but I'd like to know if there's another way around it. I am trying to put some extra logic around the DMA controller (in hardware) because I am trying to get a very specific modulation.

I really just need a way to send some parameters to a hardware register, using Python, C or sysfs is fine, IMHO. Shouldn't there be way since I already have the device tree setup with an axi-dmac controller exposed in memory?

Thank you,

Luke

For arbitrarily reading memory mapped registers of custom IP, you can just use devmen. Something like: https://gist.github.com/mr1337357/ffb73b5a1f00856b2891 You could probably do something similar in python or combine some C and python.

-Travis

Hi Travis,

Thank you again! It really did do the trick just to try reading/writing the mem dev file. I will try to use this appropriately.

Right now I am just struggling with Vivado and how to customize the AD9361_DMAC_DAC block, which I want to use to take custom commands for my modulation scheme.

Should I be manually saving off a deck of these files, or using the "IP Packaging" workflow? The reason I ask is, when I do the latter, I just get some generic DMAC block imported, and not the nice AD version that is built into the project.

Any thoughts? It's really not clear to me how to just edit one of the DMAC instances in the project without changing all of them (this includes ADC and HDMI which seems wrong).

Specifically, I want to edit (or add my own) RTL on the same level is dmac_regmap.v, but I have not found a good workflow yet.

If you have any insight, I would be very grateful.

Luke

Generally, you want package cores. It makes management and testing easier. I would just create a custom library block based on the ADI DMA or use the Xilinx one.

-Travis

Hi Travis, You have been very helpful. Could I just bug you about FPGA manager? Is it likely to be able to implement "live" FPGA image swaps? I've been re-writing the SD card each time, but I guess I'd expect live updates to be possible. Is this worth doing? Is it supported?

Hi Travis, You have been very helpful. Could I just bug you about FPGA manager? Is it likely to be able to implement "live" FPGA image swaps? I've been re-writing the SD card each time, but I guess I'd expect live updates to be possible. Is this worth doing? Is it supported?

FPGA manager is a kernel feature buts it's not maintained by ADI. So support would not come from ADI. This isn't something new as xdevcfg existed before FPGA manager. With that said it does work fine.

I personally don't really use these features since the time it takes to reboot with a new bitstream is tiny compared to synthesis. I would use it if I needed to continuous swap in different features in fabric fast. However, that is pretty rare for me.

-Travis

Hi Travis,

I have a rather odd problem now, that I was hoping you might help address.

My modulation is a simple pulse-train, and the waveform (except for the off time) is stored in memory (using python sdr.tx(dbuff) where dbuff is my np array). I am using the DMA in cyclic mode to retrieve the data, and replay it as necessary. Since I cannot store an entire pulse, I am stretching the "off time" with a counter, keyed off of "t_last" on the output streaming interface. I am basically using the "pause" bit to "stall" the pulse. It appears the DMA resumes with some uncertainty. Seeing about 2us of "jitter" between bursts. Is there some way to address this? I assume there is no good way, since the memory is shared with the CPU, but I wanted to make sure.

As an aside, I did try firing individual DMA for each pulse, but that seemed to be just as bad with the "inter-pulse" timing, or even perhaps worse.

Is there any way to make deterministically timed DMA requests on the ADRV9361z7035? Or should I be addressing a different architecture? I could see loading a custom BRAM IP and replaying that being very repeatable, but I was under the impression that the DMA would be up to this task.

Regards,

Luke

Can you create a separate thread with the connections you have made and ideally a timing diagram showing your signaling and the jitter experienced.

-Travis