KCU105 with AD9162-FMCC-EBZ: intermittent loss of JESD synchronization

Hi all,

Our design is based on JESD204B link in subclass 1 with the following parameters: Interpolation=3 | L=8 | M=2 | F=1 | S=2 | Lane rate = 10Gbps

the DAC clock frequency is 6GHz

We implemented a software application based on AD916x API Source Code Package (Rev. 1.0.0)

Regarding clock distribution, we preserved the same API configuration of clock distribution components (ADF4355 and AD9508).

In Logic side, we send a sinusoidal signal (with variable sinusoid frequency going from 10MHz to 800MHz)

In DAC side, we use the NCO modulation to shift the base band signal to higher frequencies (up to 5900MHz)

When testing on the evaluation board, we got the three following issues:

1- SYSREF event occurs after several minutes, so the link establishment takes a while (several minutes).

2- Once link establised, I tried reading IRQ status, I found that SYSREF Jitter Error is occurred. after that, SYSREF Jitter Error disappears.

3- When modifying , In high speed (each 1µs), frequencies of Baseband and NCO signals (to get frequencies higher than 2900MHz~3000MHz after NCO modulation), the JESD link synchronization is intermittently lost and the following values are read from IRQ and Links status:

JESD_IRQ_STAT_A = 0x4b

JESD_IRQ_STAT_B = 0x01

IRQ_STAT = 0x08

PLL_STAT = 0x0b

LINK_STAT0 = 0x0f

LINK_STAT1 = 0x0f

LINK_STAT2 = 0x0f

LINK_STAT3 = 0x0f

LINK_STAT4 = 0x0f

LINK_STAT5 = 0x0f

LINK_STAT6 = 0x0f

LINK_STAT7 = 0x44

CODE_GRP_SYNC = 0x7f

FRAME_SYNC = 0x7f

GOOD_CHECKSUM = 0xff

INIT_LANE_SYNC = 0x7f

But When modifying the frequecies in low speed (each second), the JESD Link keeps its synchronization.

According to some other forum answers, I found that i need to decrease SYSREF rate to reduce SYSREF jitter.

When looking to API source code, i found that OUT2 (FPGA JESD SYSREF) and OUT3 (DAC JESD SYSREF) of AD9508 are in power down mode.

i tried configuring AD9508 registers as follows to divide SYSREF rate by 8:

ad9508_register_write(0x025, 0x14);
ad9508_register_write(0x02B, 0x14);

ad9508_register_write(0x021, 7);    // to divide FPGA JESD SYSREF rate by 8
ad9508_register_write(0x027, 7);    // to divide DAC JESD SYSREF rate by 8

When testing on the board, The SYSREF event was detected in 10 to 20 seconds. but SYSREF jitter error is still occurring just after JESD Link establishment. and the JESD link synchronization is still intermittently lost.

Questions:

- Do the new AD9508 configuration of OUT2 and OUT3 affect the JESD link synchronization ?

- What are the possible causes of JESD synchronization issue in this case (use of evaluation boards and software based on reference AD916x API) ? 

- How can we debug or investigate this intermittent JESD synchronization loss issue ? 

Any help would be appreciated.

Thanks