AD9082 FMCA EBZ external clock

Hello SAH ,

AD9082/AD9081 supports direct or external clocking, this subject was discussed on those EZ threads:   Using Direct Clock on AD9081  and RE: Using an External Clock with AD9081-FMCA-EBZ .

Hope it helps!

Filip.

Thanks Filip for your reply. My question though is not about it. In AD9082 FMCA EBZ evaluation board, it's possible to feed the AD9082 chip with external clock and sysref. But according to the clocking block diagram (figure 14), these external clocks don't go to the FMC connector to feed the FPGA as well. Therefore, we have to use the other FPGA MGT clocks (out of the FMC) to get the external clock. Normally the data and clock ports of a JESD IP core should be taken from the same FPGA bank. While in this case it's not possible. I'm just wondering if the JESD IP core in the AD9082 HDL ref design is sensitive to the bank that JESD data and clock have been taken from (they must be from the same FPGA bank)? 

Thanks Filip for your reply. My question though is not about it. In AD9082 FMCA EBZ evaluation board, it's possible to feed the AD9082 chip with external clock and sysref. But according to the clocking block diagram (figure 14), these external clocks don't go to the FMC connector to feed the FPGA as well. Therefore, we have to use the other FPGA MGT clocks (out of the FMC) to get the external clock. Normally the data and clock ports of a JESD IP core should be taken from the same FPGA bank. While in this case it's not possible. I'm just wondering if the JESD IP core in the AD9082 HDL ref design is sensitive to the bank that JESD data and clock have been taken from (they must be from the same FPGA bank)? 

I don't think you need to use other FPGA MGT clock, you can use the EXT_HMCREF clock through the HMC7044 and you can feed this clock to FPGA via FMC as is shown in the Figure 20 of the EVAL-AD9081 user guide: 

If you do this setup you also have to make sure that the EXT_CLK and EXT_HMCREF are generated from the same clock source.

We have a working usecase of MxFE with External Clock for this project Stingray with a 12Ghz direct clock: https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-stingray-direct-clk.dts

Regards!

Filip.

Hello SAH ,

Do you have any updates on this topic?

Best regards,

Filip.

Hi Filip, I'm not sure if I got your point.

Let me put my question this way. Suppose that we don't want to use the on-board clock generator ( MC7044). Then we have to feed the MxFE by the EXT_CLK and EXT_SYS. There are other clocks which have to go to the FPGA. Is it possible to use other FPGA MGT clocks (from different bank) rather than the ones which are connected to the FMC of the evaluation board?

Hello SAH ,

I think you can use the USER_SMA_MGT_CLOCK_C as an external ref clock which is connected to BANK 129. In the current design BANK 229 and 228 are used for the transceivers logic through FMC0.

If you want to use this external clock this can be done only if the AD9081/AD9082 HDL design will be changed to use FMC1 connector of the ZCU102 and the entire transceiver logic will be switched to BANK129 and 130.

Best regards,

Filip.

Thank you very much Filip. 

Yes, Indeed! This looks like the actual solution. I'll try this ASAP and come back to you if I had a question.

Best,

Ali

Hello, 

do you remember if this was a proper solution for your problem? Thank you.