We're trying to reuse the ZCU102 project for the AD9083 evaluation board to be used on another carrier board (Trenz's TE0808). We were successful on generating the bitstream and we are already interfacing with the AD9083 on the platform. Up until now everything up to the Data Link layer seems to be working OK (PHY PLL is locked, and we measured both device and link clocks are generated correctly from AD9528), but we are not getting the lanes to sync to the incoming data (they are stuck in the CGS stage). Upon inspecting with an ILA core (clocked with the link clock), the data entering the Data Link Layer from the PHY seems to be OK (all "bcbcbcbc" vectors in all four lanes, phy_charisk asserted, etc), and that's when we found out that the rx IP within the axi_ad9083_rx_jesd has four 128-bit phy_data interfaces, when according to the RTL it should be only one of 128 (4x32).
The following image corresponds to the axi_ad9083_rx_jesd IP within our top level block design. The rx_phy0, 1, 2 and 3 are all 32 bit data + metadata buses coming from the PHY layer.
We think this might be the source of the issue, but the same thing happens when compiling the zcu102 project (which we assume works alright).
Any ideas on what to try next?