I have downloaded the latest HDL for ZCU102 attached with ADRV9008-1W. HDL version is for ADRV9009. I have only modified the design to have hierarchy blocks in it. After arranging the individual IP blocks into hierarchy, the design is giving critical error saying
ERROR: [Constraints 18-851] Could not find an automatically derived clock matching the supplied criteria for renaming.
I have modified the system_contr.xdc file to have proper hierarchy block name so that the respective pins can be taken correctly.
Critical Warning list
Thank you and regards
Added critical warning after the implementation
[edited by: FPGA@noob at 12:25 PM (GMT -4) on 30 Sep 2022]