ZCU102 + ADRV9009 HDL implementation fail

Question

I have downloaded the latest HDL for ZCU102 attached with ADRV9008-1W. HDL version is for ADRV9009. I have only modified the design to have hierarchy blocks in it. After arranging the individual IP blocks into hierarchy, the design is giving critical error saying ERROR: [Constraints 18-851] Could not find an automatically derived clock matching the supplied criteria for renaming. I have modified the system_contr.xdc file to have proper hierarchy block name so that the respective pins can be taken correctly. 
 
 My report_clocks 
 Critical Warning list Thank you and regards

ADIApproved · Accepted Answer

Hi, 
 As far as I know, timing violation error is the reason we are using ooc. 
 Try to keep the default ooc setting (on) and open the implemented design. There you can find the path and the name of the clock associated with the pin you are looking for. 
 However, this question is more about how Vivado handles connections and not as much about our design. Maybe take a look at some documentation from Xilinx regarding this problem if you want to learn more about the hierarchical blocks. 
 Regards.)

FPGA@noob · Answer

Hello iulia Filip_Gherman

I have opened a new thread for the question here. Please direct your answer there.
Functionality of AXI_ADCFIFO and AXI_DACFIFO with MIG Controller

Thank you for your time.

Regards,

Electronic Design Services - PartnerZone

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ZCU102 + ADRV9009 HDL implementation fail

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