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ZCU102 + ADRV9009 HDL implementation fail

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Product Number: ADRV9009 with ZCU102
Software Version: 2021_r1

I have downloaded the latest HDL for ZCU102 attached with ADRV9008-1W. HDL version is for ADRV9009. I have only modified the design to have hierarchy blocks in it. After arranging the individual IP blocks into hierarchy, the design is giving critical error saying 

ERROR: [Constraints 18-851] Could not find an automatically derived clock matching the supplied criteria for renaming.

I have modified the system_contr.xdc file to have proper hierarchy block name so that the respective pins can be taken correctly.

My report_clocks 



Critical Warning list


Thank you and regards



Added critical warning after the implementation
[edited by: FPGA@noob at 12:25 PM (GMT -4) on 30 Sep 2022]
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  • Hi, 

    From what I can see here it seems you have a naming inconsistency. I tried to build the project on my side and it was successful.

    I think you missed something when you added the hierarchy blocks. Try building it the way it without the modifications and then apply your changes, so we know where the problem comes from.

    Regards, 

    Liviu

  • Hi,
     FormerMember 
    Thanks for the reply. I have modified the design only after the make command(initial stage) have generated bit file. After that in vivado, I have changed. Could it be that the ooc parameter was on during make command but I want to generate the system design output as global and not ooc. If that is the reason, then how can I change the settings in the vivado itself or do I need to create clock in top level .xdc file?

    Thank you.

  • You can use this command  "export ADI_USE_OOC_SYNTHESIS=0" before running make. It should disable the Out of context synthesis. If this does not solve the problem, then maybe you will have to create a clock in the top level xdc file.

  • OK FormerMember  , can you give me the clock details as I don't know -period param and the name. Then I can incorporate that in the .xdc file and can try one again.

    Thank you

  • Take a look in the implemented design and see if the path you defined is right.
    clock freq is lanerate/40.

  • FormerMember  I have tried to compile the design with ooc option as 0 or "n" and there was a failure in make command stating timing constrained not met.

    Here is the log file:
    adrv9009_zcu102_vivado.log

    Thanks.

  • Hi, 

    As far as I know, timing violation error is the reason we are using ooc.

    Try to keep the default ooc setting (on) and open the implemented design. There you can find the path and the name of the clock associated with the pin you are looking for.

    However, this question is more about how Vivado handles connections and not as much about our design. Maybe take a look at some documentation from Xilinx regarding this problem if you want to learn more about the hierarchical blocks.

    Regards.

  • Hi FormerMember . I have implemented with ooc setting as on. As I don't need Tx and Rx OS blocks, I will delete them and then I can try to synthesize and implement the design as global and not as ooc .

    There is one more query for which I don't want to open a question. For DMA, I have modified the design to have ddr4_MIG and adi_adcfifo IP block attached to DMAC so that I can retrieve continuously large radio frames. Now, I want to extract, let's say 2 radio frames, from ddr4_MIG continuously and analyse it within FPGA against different parameters. Can you suggest me an IP block such as adi_dacfifio or util_dacfifo which can extract the said amount of radio frames from ddr4_MIG and fed it for analyzing again and again? During extraction of radio frames, there will be no irq request so the ddr4_MIG will have same data.

    Thank you for your time.

    Regards.

Reply
  • Hi FormerMember . I have implemented with ooc setting as on. As I don't need Tx and Rx OS blocks, I will delete them and then I can try to synthesize and implement the design as global and not as ooc .

    There is one more query for which I don't want to open a question. For DMA, I have modified the design to have ddr4_MIG and adi_adcfifo IP block attached to DMAC so that I can retrieve continuously large radio frames. Now, I want to extract, let's say 2 radio frames, from ddr4_MIG continuously and analyse it within FPGA against different parameters. Can you suggest me an IP block such as adi_dacfifio or util_dacfifo which can extract the said amount of radio frames from ddr4_MIG and fed it for analyzing again and again? During extraction of radio frames, there will be no irq request so the ddr4_MIG will have same data.

    Thank you for your time.

    Regards.

Children
  • Hello,

    At this point we haven't added support for PL DDR on the ZCU102. We typically use ADC_FIFO or Data Offload Engine HDL IP Core [Analog Devices Wiki] to capture data if the bandwidth is higher than the PS DDR can handle, but after that we send it to the PS DDR for processing. I think you have something else in mind.

    I think the PS interface for ZCU102 should handle the bandwdith coming from ADRV9009 RX channel, so you should be able to capture more than 1 GB of data. Is that enough for your use case?

    If the processing is done in the fabric, you could probably use another DMA to take the data from memory and stream it to your processing IP.

    Regards,

    Adrian

  • Hi  , thank you for your reply. I was thinking of a interconnect IP connected to MIG at one end and as subordinates, I  can have axi_adcfifo+DMAC IP cores and as another subordinate ,a xyz IP core(axi_dacfifo or util_xyzfifo), which will get the data from the MIG according to the address. As address will always be from starting of what MIG has and will go till 2 radio frames samples, so the idea is to get a IP core which can generate address, give it to MIG and according deliver the data to for e.g a custom IP core.

    I hope, my problem is understandable. Thank you

    Here is a screenshot of my DMA hierarchy

  • I think the AXI_DMAC can read data from an AXI address and stream it to a custom core.

    AXI_DACFIFO is used to get data from a DMA, store it in an PL DDR and from there forward it to a stream. As you already have the data in the memory, you don't need that. Now that i'm thinking about it, instead of getting the data from the DMA you could get it from stream directly. You could try that, but I don't think we had this use case tested.

    UTIL_adc/dacFIFOs are used with BRAM and AXI_adc/dacFIFOs are used with DDR as intermediary storage.

    Regards,

    Adrian

  • I want to get the data from ddr4 RAM which is saved there by axi_adcfifio and not from DMAC. Now, I want to extract the data from ddr4 RAM but dont know which IP core can do that.

    Regards

  • The DMAC is an IP which can take data from a memory and send it to the stream, It will be an additional DMAC, on top of the one you are already using to move data from the ADC_FIFO to the PS DDR. Is there a reason you don't want to use it ?

    Regards,

    Adrian

  • Hi   and FormerMember , sorry for late reply.
    I am posting here a screenshot of DMA where I have added DDR4 MIG and adcfifo IP cores. To that I have added additionally AXI interconnect having 2 subordinate and 1 main.
    Main is DDR4 MIG and one of the subordinate is adcfifo which writes the data in the DDR4 and another subordinate is in the question which will retrieve the data from the DDR4 and will send it to a custom IP core.

    Now, the question: If there is IP core from ADI which can be used as second subordinate to the interconnect IP core which can retrieve the data from the DDR4 through MIG.

    Regards.

  • Hello  ,

    Sorry for the late reply, there are two possible options:

    1) You can keep the original connections of the axi_adrv9009_rx_dma(basically the source of your DMA will be a FIFO interface connected with the util_cpack) and then connect axi_adcfifo_0/dma_wdata stream to your custom IP where all the captured data will be continuously streamed and your IP should determine when the frame ends.

    2) The other option is to drop the axi_adcfifo_0 from the design and replace it with a DMA that can capture data to DDR4 memory(this DMA will be configured as the existent axi_adrv9009_rx_dma, the source interface is a FIFO interface connected to the util_cpack and destination interface is a Memory-Mapped AXI connected to S00_AXI from axi_interconnect_0) and in order to extract the data from the DDR4 to a stream you can use another DMA which will be configured as TX DMA(source interface is a Memory-Mapped AXI connected to S01_AXI from axi_interconnect_0 and destination interface can be a FIFO interface or Streaming AXI connected to your IP logic). 

    The second option is more flexible from the software perspective cause you can establish when the data is written to DDR4 and when is extracted from the DDR4.

    Best regards,

    Filip.

  • Hello  ,

    Do you have any updates on this topic?

    Regards,

    Filip.

  • Hello  

    Sorry for late reply. This was pushed under due to other ongoing projects.
    Thank you for your suggestions. According to our requirements, I have taken axi_dacfifo from library/xilinx folder and there I have modified the IP core in such a way that dacfifo_rd.v is applied. Here, the core will be initiated by one of my IP core which will again collect the data from dac_data port of the modified axi_dacfifio IP core. I am struggling with the control of the IP core and was hoping if you could help me with the signals which are coming from dacfifo_wr.v but are not used as I am only reading. With what value should I iniialize them? The increment of address is done by adding arincr value but let's assume that the arincr value is 80 (in decimal format) so how much data is delivered by in each incrememnt. is it axi_size multiplied by axi_length?

    Thanks.

    Reagrds,