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Rebuilding the HDL reference of AD9082-FMCA-EBZ for ZCU102

Category: Hardware

Hi,

I have an AD9082-FMCA-EBZ evaluation board which a original boot SD card. I managed to run the evaluation setup by a Xilinx ZCU102 board, using the boot files in the SD card in folder "zynqmp-zcu102-rev10-ad9082-m4-l8-vcxo100". Note that the evaluation board has a 100MHz LO. I cloned the HDL reference design and built it as described here by this command:

make JESD_MODE=64B66B \

    RX_RATE=16.5 \

     RX_PLL_SEL=2 \

     TX_RATE=16.5 \

     TX_PLL_SEL=2 \

     REF_CLK_RATE=100 \

     RX_JESD_M=4 \

     RX_JESD_L=8 \

     RX_JESD_S=1 \

     RX_JESD_NP=16 \

     TX_JESD_M=4 \

     TX_JESD_L=8 \

     TX_JESD_S=1 \

     TX_JESD_NP=16

When I boot the board with the generated FPGA bit stream I get the following error message related to JESD configuration and the IIO doesn't work anymore.

[ 8.387594] axi-jesd204-rx 84a90000.axi-jesd204-rx: octets_per_frame * frames_per_multiframe must be a multiple of 256, got 32
[ 8.398975] axi-jesd204-rx 84a90000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_setup: Apply config Link2 failed (-22)
[ 8.409666] jesd204: /fpga-axi@0/axi-jesd204-rx@84a90000,jesd204:4,parent=84a90000.axi-jesd204-rx: JESD204[2] got error from cb: -22

I'm pretty sure that M, S and NP are correct but not sure about the reset. I need to know what exactly the make parameters should be to make the same bit file as already is embedded into the boot files in the SD card, folder  "zynqmp-zcu102-rev10-ad9082-m4-l8-vcxo100". 

Top Replies

  • Hi,

    First of all, it would be really helpful if I knew what source files are you using. I think you are talking about the 2021_R1, but I just want to be sure about that.

    Also, in the boot partition of the SD card, in the project folder you can find a text file named "make_parameters.txt" that contains the parameters required to replicate the build for that project. If that file is missing, it means that the make command was used without parameters and the project was built with the default values.

    To sum it up, if I got the version of the source files right, you only have to run "make" without having to worry about the parameters.

    Liviu.

  • Hi Liviu,

    Thanks for your reply. 

    I got the HDL reference from this git repo: https://github.com/analogdevicesinc/hdl.git

    I just use the master branch and don't checkout to any other branches.

    The file "make_parameters.txt" doesn't exist in the folder "zynqmp-zcu102-rev10-ad9082-m4-l8-vcxo100".  :-(

    But I could find similar files in other folders like "zynqmp-zcu102-rev10-ad9081". 

    When I run make without any parameters, I get JESD configuration error for parameters M, S and NP. 

    Just note that,  AD9082-FMCA-EBZ comes with two crystal oscillators (100MHz and 125MHz), I need to now the REF_CLK_RATE as well. Our board has a 100MHz LO.

  • The ref_clk_rate is by default set to 100MHz in the devicetree, so it will match your case.

    I would suggest you checkout 2021_R1 branch and try the same flow from there. In the mean time I will try to replicate your issue and give it a closer look.

  • Also, in the system_project.tcl file it is mentioned that only the 8B10B mode is supported for zcu102, so the case you presented will definitely not work.

    Please take a look at the parameters from system_project.tcl file and see what can be overwritten at make time. 

  • Yeah. You're right. I didn't checkout to 2021_r1. 

    Now, I did so and just made the project by running make without any parameter. This time I get the following error:

    [ 8.339790] axi-jesd204-rx 84a90000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_running: Link2 status failed (CGS)
    [ 8.350131] jesd204: /fpga-axi@0/axi-jesd204-rx@84a90000,jesd204:4,parent=84a90000.axi-jesd204-rx: JESD204[2] got error from cb: -1

  • Hello  

    For this JESD configuration we only have support for the following devicetree zynqmp-zcu102-rev10-ad9082-m4-l8.dts, and this will work only if you use the following make parameter for HDL: 

    JESD_MODE=8B10B
    RX_LANE_RATE=15
    TX_LANE_RATE=15
    RX_JESD_M=4
    RX_JESD_L=8
    RX_JESD_S=1
    RX_JESD_NP=16
    TX_JESD_M=4
    TX_JESD_L=8
    TX_JESD_S=1
    TX_JESD_NP=16

    As you can see for now the supported lane rate is only 15 Gbps and a 8B10B encoding, if you need support for a 64B66B encoding and a 16.5 lane rate you would need to change the devicetree accordingly!

    Best regards,

    Filip.

  • Thanks Filip,

    With these configuration, I don't get any error complaining about the JESD configuration as before. But still JESD fails to setup and boot procedure lets out these error multiple times:

    [ 9.275867] ad9081 spi1.0: JESD RX (JTX) Link2 in DATA, SYNC deasserted, PLL locked, PHASE established, MODE valid
    [ 9.367885] ad9081 spi1.0: JESD TX (JRX) Link0 0x0 lanes in DATA
    [ 9.373889] jesd204: /amba/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0] got error from cb: -1
    [ 9.383542] jesd204: /amba/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: Rolling back from 'link_enable', got error -1

    .

    .[   10.787462] jesd204: /amba/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: FSM completed with error -1

    I'm pretty sure that still the JESD configuration is not compatible with the Linux kernel which is packed into BOOT image in folder "zynqmp-zcu102-rev10-ad9082-m4-l8-vcxo100". 

    I would be grateful if you help since this is really blocking at the moment.

  • Hello  ,

    I'm not sure what devicetree are you using at this moment, you can try to build the devicetree that I mentioned in my last message, you can follow this tutorial on how to build the devicetree for zynqMP https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/linux/zynqmp. I also tried this configuration on my side and it worked fine.

    Regards,

    Filip.

  • Yes! I use the same devicetree. Maybe the way I make the Petalinux boot image is not correct. How can I repack the new XSA file with Linux kernel to make a boot image? At the moment, I just manually (by a matlab script) replace the binary of Partition 2 of BOOT.BIN  file that I get from folder "zynqmp-zcu102-rev10-ad9082-m4-l8-vcxo100". I do this as I don't have the Petalinux project including the boot and drivers which are compatible with IIO oscilloscopic.

  • In my opinion, you can try to format your SD card and then install the latest Kuiper Image https://wiki.analog.com/resources/tools-software/linux-software/adi-kuiper_images/release_notes and then retry to boot the system using the files from the SD card, you will find this project in the boot partition.