AD9371 & ZCU102 related questions

Hello Mahima,

The link_clk you've highlighted is driven by axi_ad9371_tx_clkgen/clk_0, which is a 125MHz clk.

The axi_ad9371_tx_clkgen has an input clock of 125MHz, VCO_MUL is set to 8, and CLK0_DIV is also set to 8, so the frequency of the clk0_div is 125MHz.
These parameters are set here: https://github.com/analogdevicesinc/hdl/blob/master/projects/adrv9371x/common/adrv9371x_bd.tcl#L56.

For more details upon the axi_clkgen, here is the wiki page: https://wiki.analog.com/resources/fpga/docs/axi_clkgen.

Kind Regards,
Stanca

The above clock rate is the maximum rate, for maximum bandwith. Depending on the exact iio profile that is selected, the link clocks will be changed.

In most of our projects, the link clk is computed as: link_clk = lane_rate / 40.

Thank you for the reply.

One more question i have

In the following block, how does tpl_core generates enable[3:0] and dac_valid[3:0] ? As i have seen it is driving tx_fir_interpolator block.

For JESD204 TPL for DAC, here you may find a brief description of the Signal and Interface Pins along with a Block Diagram.

If you take a look at the ad_ip_jesd204_tpl_dac_core.v, you may notice that the enable signal for every channel that is selected is driven by the jesd204_tpl_dac_channel.v.

The valid signal depends on the dac_sync_armed signal, which is not used in this case, meaning that dac_valid will be set to 1.

Thank you for the reply.

As far as i have understood from design, transmit data is coming in this format

m_axis_data = {Q1_S1,I1_S1,Q0_S1,I0_S1, Q1_S0,I1_S0,Q0_S0,I0_S0}

Basically at every clock, we are getting 2 samples (dac_data_0 and dac_data_2) of first TX channel and 2 samples(dac_data_1 and dac_data_3) of second TX channel.

May i know which and how samples will be used by ad9371 IC as it has 2 DACs ?

Hello,

In this link  RE: question about ad9371 hdl reference design in Tx chain

It is mentioned like this

The 128-bit data will have the following structure (MSB first):

{TX2_Q_1, TX2_Q_0, TX2_I_1, TX2_I_0, TX1_Q_1, TX1_Q_0, TX1_I_1, TX1_I_0}

So, hence after util_ad9371_tx_upack, fifo_rd_data_0[31:0] contains TX1_I data which is 32 bit wide

And, fifo_rd_data_1[31:0] :- TX1_Q (32 bit wide)

And, fifo_rd_data_2[31:0] :- TX2_I (32 bit wide)

And, fifo_rd_data_3[31:0] :- TX2_Q (32 bit wide)

Is the above understanding correct ? If yes, which samples will be used by AD9371 DAC ? Please clarify my doubts

Hello,

mahima90 said:

So, hence after util_ad9371_tx_upack, fifo_rd_data_0[31:0] contains TX1_I data which is 32 bit wide

And, fifo_rd_data_1[31:0] :- TX1_Q (32 bit wide)

And, fifo_rd_data_2[31:0] :- TX2_I (32 bit wide)

And, fifo_rd_data_3[31:0] :- TX2_Q (32 bit wide)

Yes, the above order is correct, but the 32 bit is actually 2 subsequent samples for that converter. The RF output will be generated by mixing the I and Q signals. (please see Figure 1 of AD9371 datasheet).

Regards,

Stanca

Thank you for the reply.

I have to add Xilinx CFR and Xilinx DPD IP in this RTL design. CFR accepts 16 bit I and 16 bit Q data.

How should i proceed? Do you recommend me to use xlslice ?

OR

Can i change axi_ad9371_tx_dma -> destination bus width to 64 ? In this way, at every clock cycle, we will get one sample.

I suppose you are using the default JESD configuration for this design, with TX_JESD_M = 4 and TX_JESD_L = 4. If you are limited to 16bit I and Q data and you need one sample/clock, I'd recommend changing the number of lanes per link to 2. This can be done either in system_project.tcl or from the terminal when building the design (e.g. make TX_JESD_L=2).

Thsnk you for the reply. I will try to change the number of lane per link to 2.