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Synchronisation of JESD204B sysref between link layer receive peripherals

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I have a signal acquisition system that uses 2 AD9695. The output of the ADCs must be aligned with the help of sysref signal (JESD204B subclass 1 operation) . The ADCs are confugured to ramp test mode (Register 0x550 set to "1111")

The sysref signal is synchronized to local clock separately in each receive inside jesd204_lmfc module. I understand that this was done for user convenience. However, this leads to different timing paths from input buffer to the synchronisation circuit which may be problematic.

In attempt to counteract it I first tried to limit the latency to the synchronizer with timing constraints:

set_max_delay  [get_property PERIOD [get_clocks -of_objects [get_ports  clk]]]   -to [get_pins sysref_r_reg/D] 

This, however, didn't work reliably. Sometimes (after system reset) the synchronised sysref signals went out of alignment, which resulted in misaligned LMFC and therefore misaligned ADC sample  values.

I also tried solution of the problem with registers placed in IO banks (as in the constraints that AD dilevers with the peripheral)

set_property IOB true [get_cells {sysref_r_reg}] 

this produced even worse result, sysref went out of alignment very often

The only real solution to is to put the synchronizer in front of the peripherals and feed already synchronized sysref to the peripherals. However this adds additional latency to sysref and I wonder whether this might have any adverse effects?

[edited by: Quant at 4:02 PM (GMT -4) on 27 Sep 2022]
  • Hello,

    Are you using our JESD204 Interface Framework as IPs for JESD204 ? If so, you could use a single IP for both ADCs.

    Have you seen hdl/projects/ad9208_dual_ebz at master · analogdevicesinc/hdl ( AD9208-DUAL-EBZ HDL reference design [Analog Devices Wiki] ?

    Can you describe clocking in your system ?

    Regarding adding synchronizer in front of the peripherals, I don't see an issue with the additional latency.



  • Yes I use AD link layer as well as transport transport layer peripherals. Xilinx JESD204 PHY IP core is used for physical layer.

    The hardware for the data acquisition and processing was supplied by an external vendor. It consists of a MicroTCA FPGA (Kintex Ultrascale) carrier board with AMC connector (includes PCIe Link) and FMC breakout board with a pair of AD9695. The clocks for the ADC and JESD204B are generated on the board and come from separate but aligned outputs of LMK. Therefore the FPGA has 2 major clock domains: one that is synchronous to incoming data/JESD204 link and one that is synchronous to PCI-E link.

    The common synchroniser solved the misalignment problem, and since it has no ill effects, I will stick with it for now.

    The documentation is a bit confusing regarding using the same peripheral for multiple chips, especially with separate PHY cores, that may have different start up times. It is also a bit clearer to have separate decoding chain for each ADC. But I will consider to use common peripherals in the future.