Hi ADI Team,
We have zc706 eval board + ADRV9008-1W setup using ADI HDL as the base FPGA Design with Linux Kuiper. We want to save 4 radio frames and analyze them in FPGA but as the data is around 9.8 MB, we won't be able to store it in BRAM. We were thinking of using DDR which is there in the eval board for FPGA and extracting the data from it and analysing it in the design. Through this, we will not only have zero lag data but also the data can be extracted from more than 4 radio frames. For this reason which IP cores can be used? We were thinking of axi_dacfifo+ util_upack, from util_upack the data can be extracted. Would this method be correct?
Please note that in the design we are having axi_adcfifo which was added according to our need.
Thank you for your time.