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AD9213 ADI JESD204B Transport Layer Output Issues

Category: Hardware
Software Version: Vivado 2019.1

Hi Team, 

                We are developing drivers for VCU118(Xilinx Virtex Ultrascale Plus) and HTG-FMC-AD9213(12 ADC)-AD9172(16 DAC).For developing drivers for AD9213 with VCU118, we used AD9208 as our reference design. The AD9213 ADC I'm using at 10Gsps sampling rate. The lane rate is 12.5Gbps, L=16, M=1(real ADC) , S =16 ,  F =2 , N = NP =16 ,  K =32, Full Bandwidth Mode, Subclass 1. fs = 10Gsps, FPGA_REF_CLK = lane rate / 40 = 312.5MHz ,  FPGA_DEV_CLK = lane rate/20 = 312.5MHz. In the HTG-AD9213 ADC , there is ADF4371 PLL which generates a 10GHz clock for ADC. The HMC7044 PLL is generating the FPGA_REF_CLK , FPGA_SYSREF and ADC_SYSREF. The SYSREF frequency = ADC Clock /2048 = 4.88MHz.The FPGA_DEV_CLK is the rx_out_clk of util_adxcvr block. 
 The JESD204B Link status is DATA, and JESD204B PLL is locked.
 But the  ADC output of JESD204B transport layer is noise(fixed pattern) which is constant and not changing run to run in the chip scope(ILA). While giving external input to ADC , it won't change. The random pattern is fixed in the chip scope and not updating run to run. I also run test patterns using 0x505 register (Alternate checker mode, 1/0 toggle word ) and the TPL outputs are observed correctly but those outputs are also fixed and not changing run to run in the chipscope (ILA). Can you please guide me with this. 
Here I'm attaching the ADC output data : 
Thanks in Advance
Goli Ganesh

Top Replies

  • Hi  ,

                

                                        Sorry for the late reply. Currently no updates for that issue. I'm stuck at that point. Now, I'm trying with Xilinx JESD IP instead of using ADI JESD  and also…
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