Hi AdrianC ,
1. The JESD204B link is stable.
2. Yes, we tried setting ramp mode. But the output is not changing run to run in the chipscope(ILA). The test patterns are generating properly but they are also not changing run to run in the chipscope. Is there any API's for AD9213? Why the TPL core data is not changing run to run in the chipscope and why it is fixed to constant data?
Thanks and Regards
We have a dual AD9213 design available, but it's specific to Stratix 10 and we have it working with Linux (see analogdevicesinc/linux at altera_adxcvr (github.com)). The HDL is on master so the TPL handles the case correctly.
I think we tried discussing regarding this in several EZ threads, but because we don't have hardware for Xilinx, it's hard to debug.
My first thought is that the link is not entirely stable, so maybe the settings for the transceivers are not entirely correct. Maybe you can check them by going through the following guide:
Does the data from the data link layer change ?
Can you try setting the ramp by:
Set 0x503 bit 5 to 1
Set 0x505 to 0x8
Hi AdrianC ,
Sorry for the late reply. Actually I tried setting the ramp the same way as you mentioned above, but I had the same issue. I already used the xilinx FPGAs Transceivers Wizard, based on that only I configured the util_adxcvr block. Now I'm trying for lower sample rates. If I find anything I will update you.
Thanks in Advance