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Dynamic partial reconfiguration using ADRV9361-Z7035 + ADRV1CRR-FMC

Category: Software
Product Number: ADRV9361-Z7035 + ADRV1CRR-FMC
Software Version: Vivado 2021.2

Hello,

We are trying to implement the dynamic partial reconfiguration processes on ADRV9361-Z7035 + ADRV1CRR-FMC board, we don't know exactly how to build the block design of this system on VIVADO 2021.2 that makes it possible to transmit and receive I and Q data between FPGA and AD9361 transceiver based on the reconfigurable modulation technique in the reconfigurable partition. we find an example of doing that but the hardware is FMCOMM2 and the tool is VIVADO 2014 https://wiki.analog.com/resources/fpga/docs/hdl/partial , we have tried to do this example but we got errors during the synthesis process. In addition, this example is not clear regarding the sequence of the execution of the TCL file. for example, we don't know which TCLfile we have to run first adi_prcfg_project.tcl or system_project.tcl and when we have to run prcfg_setup.tcl.. we tried to run adi_prcfg_project.tcl first but it didn't execute.

Does there a clear example for implementing dynamic partial reconfiguration on ADRV9361-Z7035 + ADRV1CRR-FMC board using VIVADO 2021.2?

Thanks in advance

Top Replies

    •  Analog Employees 
    •  Super User 
    Sep 29, 2022 +1 verified

    Hello  ,

    I looked deeper into this issue and it seems that we cannot offer support for partial reconfiguration at this moment. I can give you limited help in this direction, BUT I am not familiar with…

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  • Hello  ,

    I looked deeper into this issue and it seems that we cannot offer support for partial reconfiguration at this moment. I can give you limited help in this direction, BUT I am not familiar with it, thus I cannot guarantee the success of this project.

    What branch did you use when building the project? I suppose master?
    If so, please use hdl_2021_r1 (and Vivado 2021.1) since this is the latest stable branch and the projects from here are tested and are working. The master branch is unstable.

    Can you open a console, go to the folder of your project and run make there? Like it's done here. And to tell me what you get.

    Afterwards, I would run adi_prcfg_project.tcl, but it needs some adaptations, since this is an old script and our projects have changed and tools also. Now we use Xilinx Vitis and not SDK anymore (here if you see, it creates SDK folders, and it has to be modified).

    After building the project, I think you should change the script to adapt it to our current structure.

    Regards,
    Iulia

Reply
  • Hello  ,

    I looked deeper into this issue and it seems that we cannot offer support for partial reconfiguration at this moment. I can give you limited help in this direction, BUT I am not familiar with it, thus I cannot guarantee the success of this project.

    What branch did you use when building the project? I suppose master?
    If so, please use hdl_2021_r1 (and Vivado 2021.1) since this is the latest stable branch and the projects from here are tested and are working. The master branch is unstable.

    Can you open a console, go to the folder of your project and run make there? Like it's done here. And to tell me what you get.

    Afterwards, I would run adi_prcfg_project.tcl, but it needs some adaptations, since this is an old script and our projects have changed and tools also. Now we use Xilinx Vitis and not SDK anymore (here if you see, it creates SDK folders, and it has to be modified).

    After building the project, I think you should change the script to adapt it to our current structure.

    Regards,
    Iulia

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