We are trying to implement the dynamic partial reconfiguration processes on ADRV9361-Z7035 + ADRV1CRR-FMC board, we don't know exactly how to build the block design of this system on VIVADO 2021.2 that makes it possible to transmit and receive I and Q data between FPGA and AD9361 transceiver based on the reconfigurable modulation technique in the reconfigurable partition. we find an example of doing that but the hardware is FMCOMM2 and the tool is VIVADO 2014 https://wiki.analog.com/resources/fpga/docs/hdl/partial , we have tried to do this example but we got errors during the synthesis process. In addition, this example is not clear regarding the sequence of the execution of the TCL file. for example, we don't know which TCLfile we have to run first adi_prcfg_project.tcl or system_project.tcl and when we have to run prcfg_setup.tcl.. we tried to run adi_prcfg_project.tcl first but it didn't execute.
Does there a clear example for implementing dynamic partial reconfiguration on ADRV9361-Z7035 + ADRV1CRR-FMC board using VIVADO 2021.2?
Thanks in advance