Post Go back to editing

Dynamic partial reconfiguration using ADRV9361-Z7035 + ADRV1CRR-FMC

Category: Software
Product Number: ADRV9361-Z7035 + ADRV1CRR-FMC
Software Version: Vivado 2021.2

Hello,

We are trying to implement the dynamic partial reconfiguration processes on ADRV9361-Z7035 + ADRV1CRR-FMC board, we don't know exactly how to build the block design of this system on VIVADO 2021.2 that makes it possible to transmit and receive I and Q data between FPGA and AD9361 transceiver based on the reconfigurable modulation technique in the reconfigurable partition. we find an example of doing that but the hardware is FMCOMM2 and the tool is VIVADO 2014 https://wiki.analog.com/resources/fpga/docs/hdl/partial , we have tried to do this example but we got errors during the synthesis process. In addition, this example is not clear regarding the sequence of the execution of the TCL file. for example, we don't know which TCLfile we have to run first adi_prcfg_project.tcl or system_project.tcl and when we have to run prcfg_setup.tcl.. we tried to run adi_prcfg_project.tcl first but it didn't execute.

Does there a clear example for implementing dynamic partial reconfiguration on ADRV9361-Z7035 + ADRV1CRR-FMC board using VIVADO 2021.2?

Thanks in advance

Top Replies

  • Hello  ,

    I looked deeper into this issue and it seems that we cannot offer support for partial reconfiguration at this moment. I can give you limited help in this direction, BUT I am not familiar with…

  • This should be a question for the https://ez.analog.com/fpga community.

    Thanks,
    Dragos 

  • But this link is for the same page I had asked my question (FPGA Reference Designs ) !!

  •  Hello  ,

    Can you share with us the log, to see if Vivado says what went wrong? And if you can give us some more details on what you adapted, starting from this wiki page example.
    Also, did you follow the steps from here (and the links from that paragraph too)?

    Regards,
    Iulia

  • Hello Iulia,

    Thanks for your participation in solving the issue.

    I had followed these steps:

    1- Open VIVADO 2021.2 and change the directory of the project to where the folder named adrv9361z7035 is located.

    2- Run adi_make.tcl

    3- Build all libraires using adi_make::lib all command

    4- Build axi_dmac  IP using adi_make::lib axi_dmac

    5- Run adi_make::lib jesd204/jesd204_rx

    6- Run system_project.tcl

    VIVADO succeed in executing steps 1,2,4,5 but failed to execute step 3 and gave an error as in the attached file at line no. 1573, and step 6 and gave an error as in attached file line no. 3111 and 3112.

    I followed the instructions in the link you shared, and got the above errors.

    I also don’t know in which step I have to run adi_prcfg_project.tcl script which arranges the folder structure of the project and executes the partial reconfiguration processes?

    I attached all the tcl console commands and its results

    Regards,

    Elhady

    start_gui
    cd D:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/projects/adrv9361z7035/ccfmc_lvds_me/
    source D:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/projects/scripts/adi_make.tcl
    # namespace eval adi_make {
    #   ##############################################################################
    #   # to print debug step messages "set debug_msg=1" (set adi_make::debug_msg 1)
    #   variable debug_msg 0
    #   ##############################################################################
    # 
    #   variable library_dir
    #   variable PWD [pwd]
    #   variable root_hdl_folder
    #   variable done_list ""
    #   variable indent_level ""
    # 
    #   # get library absolute path
    #   set root_hdl_folder ""
    #   set glb_path $PWD
    #   if { [regexp projects $glb_path] } {
    #     regsub {/projects.*$} $glb_path "" root_hdl_folder
    #   } else {
    #     puts "ERROR: Not in hdl/* folder"
    #     return
    #   }
    # 
    #   set library_dir "$root_hdl_folder/library"
    # 
    #   #----------------------------------------------------------------------------
    #   # have debug messages
    #   proc puts_msg { message } {
    #     variable debug_msg
    #     variable indent_level
    #     if { $debug_msg == 1 } {
    #       puts $indent_level$message
    #     }
    #   }
    # 
    #   #----------------------------------------------------------------------------
    #   # returns the projects required set of libraries
    #   proc get_libraries {} {
    # 
    #     set build_list ""
    # 
    #     set search_pattern "LIB_DEPS.*="
    #     set fp1 [open ./Makefile r]
    #     set file_data [read $fp1]
    #     close $fp1
    # 
    #     set lines [split $file_data \n]
    #     foreach line $lines {
    #       if { [regexp $search_pattern $line] } {
    #         regsub -all $search_pattern $line "" library
    #         set library [string trim $library]
    #         puts_msg "\t- project dep: $library"
    #         append build_list "$library "
    #       }
    #     }
    #     return $build_list
    #   }
    # 
    #   #----------------------------------------------------------------------------
    #   proc lib { libraries } {
    # 
    #     variable library_dir
    #     variable PWD
    #     variable done_list
    # 
    #     set build_list $libraries
    #     if { $libraries == "all" } {
    #       set build_list "[get_libraries]"
    #     }
    # 
    #     set libraries ""
    #     puts "Building:"
    #     foreach b_lib $build_list {
    #       puts "- $b_lib"
    #       append libraries "$library_dir/$b_lib "
    #     }
    # 
    #     puts "Please wait, this might take a few minutes"
    # 
    #     # searching for subdir libraries in path of the given args
    #     set first_lib [lindex $libraries 0]
    #     if { $first_lib == "" } {
    #      set first_lib "."
    #     }
    #     # getting all (libraries)
    #     set index 0
    #     set library_element(1) $first_lib
    #     foreach argument $libraries {
    #      incr index 1
    #      set library_element($index) $argument
    #     }
    # 
    #     # search for all possible IPs in the given argument paths
    #     set makefiles ""
    #     if { $index == 0 } {
    #       set index 1
    #     }
    #     for {set y 1} {$y<=$index} {incr y} {
    #       set dir "$library_element($y)/"
    #       #search 4 level subdirectories for Makefiles
    #       for {set x 1} {$x<=4} {incr x} {
    #       catch { append makefiles " [glob "${dir}Makefile"]" } err
    #         append dir "*/"
    #       }
    #     }
    # 
    #     if { $makefiles == "" } {
    #       puts "ERROR: Wrong path to IP or the IP does not have a Makefile starting from \"$library_element(1)\""
    #     }
    # 
    #     # filter out non buildable libs (non *_ip.tcl)
    #     set buildable ""
    #     foreach fs $makefiles {
    #       set lib_dir [file dirname $fs]
    #       set lib_name "[file tail $lib_dir]_ip.tcl"
    #       if { [file exists $lib_dir/$lib_name] } {
    #         append buildable "$fs "
    #       }
    #     }
    #     set makefiles $buildable
    # 
    #     # build all detected IPs
    #     foreach fs $makefiles {
    #       regsub /Makefile $fs "" fs
    #       if { $fs == "." } {
    #         set fs [string trim [file tail [file normalize $fs]]]
    #       }
    #       regsub .*library/ $fs "" fs
    #       build_lib $fs
    #     }
    # 
    #     cd $PWD
    #     set done_list ""
    #   }
    # 
    #   #----------------------------------------------------------------------------
    #   # IP build procedure
    #   proc build_lib { library } {
    # 
    #     variable done_list
    #     variable library_dir
    #     variable indent_level
    # 
    #     append indent_level "\t" ;# debug messages
    # 
    #     puts_msg "DEBUG build_lib proc (recursive called)"
    # 
    #     # determine if the IP was previously built in the current adi_make_lib.tcl call
    #     if { [regexp $library $done_list] } {
    #       puts_msg "> Build previously done on $library"
    #       regsub . $indent_level "" indent_level
    #       return
    #     } else {
    #       puts_msg "- Start build of $library"
    #     }
    #     puts_msg "- Search dependencies for $library"
    # 
    #     # search for current IP dependencies
    # 
    #     # define library dependency search (Makefiles)
    #     set serch_pattern "XILINX_.*_DEPS.*="
    #     set dep_list ""
    # 
    #     set fp1 [open $library_dir/$library/Makefile r]
    #     set file_data [read $fp1]
    #     close $fp1
    # 
    #     set lines [split $file_data \n]
    #     foreach line $lines {
    #       if { [regexp $serch_pattern $line] } {
    #         regsub -all $serch_pattern $line "" lib_dep
    #         set lib_dep [string trim $lib_dep]
    #         puts_msg "\t$library is dependent on $lib_dep"
    #         append dep_list "$lib_dep "
    #       }
    #     }
    # 
    #     foreach lib $dep_list {
    #       build_lib $lib
    #     }
    # 
    #     puts_msg "- Continue build on $library"
    #     set lib_name "[file tail $library]_ip"
    # 
    #     cd $library_dir/${library}
    #     exec vivado -mode batch -source "$library_dir/${library}/${lib_name}.tcl"
    #     file copy -force ./vivado.log ./${lib_name}.log
    #     puts "- Done building $library"
    #     append done_list $library
    #     regsub . $indent_level "" indent_level
    #   }
    # 
    #   #----------------------------------------------------------------------------
    #   # boot_bin build procedure
    #   proc boot_bin {} {
    # 
    #     variable root_hdl_folder
    # 
    #     set arm_tr_sw_elf "bl31.elf"
    #     set boot_bin_folder "boot_bin"
    #     if {[catch {set xsa_file "[glob "./*.sdk/system_top.xsa"]"} fid]} {
    #       puts stderr "ERROR: $fid\n\rNOTE: you must have built hdl project\n\
    #       \rSee: https://wiki.analog.com/resources/fpga/docs/build\n"
    #       return
    #     }
    #     if {[catch {set uboot_elf "[glob "./u-boot*.elf"]" } fid]} {
    #       puts stderr "ERROR: $fid\n\rNOTE: you must have a the u-boot.elf in [pwd]\n\
    #       \rSee: https://wiki.analog.com/resources/fpga/docs/build\n"
    #       return
    #     }
    # 
    #     puts "root_hdl_folder $root_hdl_folder"
    #     puts "uboot_elf $uboot_elf"
    #     puts "xsa_file $xsa_file"
    # 
    #     # determine if Xilinx SDK tools are set in the enviroment
    #     package require platform
    #     set os_type [platform::generic]
    #     if { [regexp ^win $os_type] } {
    #       set w_cmd where
    #     } elseif { [regexp ^linux $os_type] } {
    #       set w_cmd which
    #     } else {
    #       puts "ERROR: Unknown OS: $os_type"
    #       exit 1
    #     }
    #     set xsct_loc [exec $w_cmd xsct]
    # 
    #     # search for Xilinx Command Line Tool (SDK)
    #     if { $xsct_loc == "" } {
    #       puts $env(PATH)
    #       puts "ERROR: SDK not installed or it is not defined in the enviroment path"
    #       exit 1
    #     }
    # 
    #     set xsct_script "exec xsct $root_hdl_folder/projects/scripts/adi_make_boot_bin.tcl"
    #     set build_args "$xsa_file $uboot_elf $boot_bin_folder $arm_tr_sw_elf"
    #     puts "Please wait, this may take a few minutes."
    #     eval $xsct_script $build_args
    #   }
    # 
    # } ;
    adi_make::lib all
    Building:
    - axi_ad9361
    - axi_clkgen
    - axi_dmac
    - axi_gpreg
    - axi_hdmi_tx
    - axi_i2s_adi
    - axi_spdif_tx
    - util_clkdiv
    - util_cpack
    - util_rfifo
    - util_tdd_sync
    - util_upack
    - util_wfifo
    - xilinx/axi_xcvrlb
    Please wait, this might take a few minutes
    
    ****** Vivado v2021.2 (64-bit)
      **** SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
      **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
        ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
    
    source D:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361/axi_ad9361_ip.tcl
    # source ../scripts/adi_env.tcl
    ## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
    ## set ad_phdl_dir $ad_hdl_dir
    ## if [info exists ::env(ADI_HDL_DIR)] {
    ##   set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
    ## }
    ## if [info exists ::env(ADI_PHDL_DIR)] {
    ##   set ad_phdl_dir [file normalize $::env(ADI_PHDL_DIR)]
    ## }
    # source $ad_hdl_dir/library/scripts/adi_ip.tcl
    ## if {![info exists REQUIRED_VIVADO_VERSION]} {
    ##   #set REQUIRED_VIVADO_VERSION "2017.4.1"
    ##   set REQUIRED_VIVADO_VERSION "2021.2"
    ## }
    ## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
    ##   set IGNORE_VERSION_CHECK 1
    ## } elseif {![info exists IGNORE_VERSION_CHECK]} {
    ##   set IGNORE_VERSION_CHECK 0
    ## }
    ## proc adi_ip_ttcl {ip_name ip_constr_files} {
    ## 
    ##   set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
    ##   set f [ipx::add_file $ip_constr_files $proj_filegroup]
    ##   set_property -dict [list \
    ##     type ttcl \
    ##   ] $f
    ## }
    ## proc adi_ip_bd {ip_name ip_bd_files} {
    ##   set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
    ##   if {$proj_filegroup == {}} {
    ##     set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
    ##   }
    ##   set f [ipx::add_file $ip_bd_files $proj_filegroup]
    ##   set_property -dict [list \
    ##     type tclSource \
    ##   ] $f
    ## }
    ## proc adi_ip_infer_streaming_interfaces {ip_name} {
    ## 
    ##   ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
    ## 
    ## }
    ## proc adi_ip_infer_mm_interfaces {ip_name} {
    ## 
    ##   ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
    ## 
    ## }
    ## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
    ##   foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
    ##     set_property ENABLEMENT_DEPENDENCY $dependency $port
    ##     if {$driver_value != {}} {
    ##       set_property DRIVER_VALUE $driver_value $port
    ##     }
    ##   }
    ## }
    ## proc adi_set_bus_dependency {bus prefix dependency} {
    ##   set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
    ##   adi_set_ports_dependency $prefix $dependency
    ## }
    ## proc adi_add_port_map {bus phys logic} {
    ##   set map [ipx::add_port_map $phys $bus]
    ##   set_property "PHYSICAL_NAME" $phys $map
    ##   set_property "LOGICAL_NAME" $logic $map
    ## }
    ## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
    ##   set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
    ## 
    ##   set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
    ##   set_property "BUS_TYPE_VLNV" $bus_type $bus
    ##   set_property "INTERFACE_MODE" $mode $bus
    ## 
    ##   foreach port_map $port_maps {
    ##     adi_add_port_map $bus {*}$port_map
    ##   }
    ## }
    ## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
    ##   for {set i 0} {$i < 8} {incr i} {
    ##     set bus_name [format "%s%d" $bus_name_prefix $i]
    ##     set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
    ## 
    ##     set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
    ##     set_property "BUS_TYPE_VLNV" $bus_type $bus
    ##     set_property "INTERFACE_MODE" $mode $bus
    ## 
    ##     if {$dependency ne ""} {
    ##       set bus_dependency [string map [list "{i}" $i] $dependency]
    ##       set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
    ##     }
    ## 
    ##     foreach port_map $port_maps {
    ##       lassign $port_map phys logic width
    ##       set map [ipx::add_port_map $phys $bus]
    ##       set_property "PHYSICAL_NAME" $phys $map
    ##       set_property "LOGICAL_NAME" $logic $map
    ##       set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
    ##       set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
    ##     }
    ##   }
    ## }
    ## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
    ##   set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
    ##   set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
    ##   set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
    ##   set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
    ##   set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
    ##   set_property display_name $clock_inf_name $clock_inf
    ##   set clock_map [ipx::add_port_map "CLK" $clock_inf]
    ##   set_property physical_name $clock_signal_name $clock_map
    ## 
    ##   set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
    ##   set_property value $bus_inf_name $assoc_busif
    ## 
    ##   if { $reset_signal_name != "" } {
    ##     set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
    ##     set_property value $reset_signal_name $assoc_reset
    ## 
    ##     set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
    ##     set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
    ##     set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
    ##     set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
    ##     set_property display_name $reset_inf_name $reset_inf
    ##     set_property interface_mode $reset_signal_mode $reset_inf
    ##     set reset_map [ipx::add_port_map "RST" $reset_inf]
    ##     set_property physical_name $reset_signal_name $reset_map
    ## 
    ##     set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
    ##     if {[string match {*[Nn]} $reset_signal_name] == 1} {
    ##       set_property value "ACTIVE_LOW" $reset_polarity
    ##     } else {
    ##       set_property value "ACTIVE_HIGH" $reset_polarity
    ##     }
    ##   }
    ## }
    ## proc adi_ip_add_core_dependencies {vlnvs} {
    ##   foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
    ##     foreach vlnv $vlnvs {
    ##       ipx::add_subcore $vlnv $file_group
    ##     }
    ##   }
    ## }
    ## variable ip_constr_files
    ## proc adi_ip_create {ip_name} {
    ## 
    ##   global ad_hdl_dir
    ##   global ad_phdl_dir
    ##   global ip_constr_files
    ##   global REQUIRED_VIVADO_VERSION
    ##   global IGNORE_VERSION_CHECK
    ## 
    ##   set VIVADO_VERSION [version -short]
    ##   if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
    ##     puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
    ##     puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
    ##     puts -nonewline "got $VIVADO_VERSION.\n"
    ##   }
    ## 
    ##   create_project $ip_name . -force
    ## 
    ##   ## Load custom message severity definitions
    ##   source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
    ## 
    ##   set ip_constr_files ""
    ##   set lib_dirs $ad_hdl_dir/library
    ##   if {$ad_hdl_dir ne $ad_phdl_dir} {
    ##     lappend lib_dirs $ad_phdl_dir/library
    ##   }
    ## 
    ##   set_property ip_repo_paths $lib_dirs [current_fileset]
    ##   update_ip_catalog
    ## }
    ## proc adi_ip_files {ip_name ip_files} {
    ## 
    ##   global ip_constr_files
    ## 
    ##   set ip_constr_files ""
    ##   foreach m_file $ip_files {
    ##     if {[file extension $m_file] eq ".xdc"} {
    ##       lappend ip_constr_files $m_file
    ##     }
    ##   }
    ## 
    ##   set proj_fileset [get_filesets sources_1]
    ##   add_files -norecurse -scan_for_includes -fileset $proj_fileset $ip_files
    ##   set_property "top" "$ip_name" $proj_fileset
    ## }
    ## proc adi_ip_properties_lite {ip_name} {
    ## 
    ##   global ip_constr_files
    ## 
    ##   ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
    ##   set_property name $ip_name [ipx::current_core]
    ##   set_property vendor_display_name {Analog Devices} [ipx::current_core]
    ##   set_property company_url {http://www.analog.com} [ipx::current_core]
    ## 
    ##   set i_families ""
    ##   foreach i_part [get_parts] {
    ##     lappend i_families [get_property FAMILY $i_part]
    ##   }
    ##   set i_families [lsort -unique $i_families]
    ##   set s_families [get_property supported_families [ipx::current_core]]
    ##   foreach i_family $i_families {
    ##     set s_families "$s_families $i_family Production"
    ##     set s_families "$s_families $i_family Beta"
    ##   }
    ##   set_property supported_families $s_families [ipx::current_core]
    ##   ipx::save_core
    ## 
    ##   ipx::remove_all_bus_interface [ipx::current_core]
    ##   set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
    ##   foreach map $memory_maps {
    ##     ipx::remove_memory_map [lindex $map 2] [ipx::current_core ]
    ##   }
    ##   ipx::save_core
    ## 
    ##   set i_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
    ##   foreach i_file $ip_constr_files {
    ##     set i_module [file tail $i_file]
    ##     regsub {_constr\.xdc} $i_module {} i_module
    ##     ipx::add_file $i_file $i_filegroup
    ##     set_property SCOPED_TO_REF $i_module [ipx::get_files $i_file -of_objects $i_filegroup]
    ##   }
    ##   ipx::save_core
    ## }
    ## proc adi_ip_properties {ip_name} {
    ## 
    ##   adi_ip_properties_lite $ip_name
    ## 
    ##   ipx::infer_bus_interface {\
    ##     s_axi_awvalid \
    ##     s_axi_awaddr \
    ##     s_axi_awprot \
    ##     s_axi_awready \
    ##     s_axi_wvalid \
    ##     s_axi_wdata \
    ##     s_axi_wstrb \
    ##     s_axi_wready \
    ##     s_axi_bvalid \
    ##     s_axi_bresp \
    ##     s_axi_bready \
    ##     s_axi_arvalid \
    ##     s_axi_araddr \
    ##     s_axi_arprot \
    ##     s_axi_arready \
    ##     s_axi_rvalid \
    ##     s_axi_rdata \
    ##     s_axi_rresp \
    ##     s_axi_rready} \
    ##   xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
    ## 
    ##   ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
    ##   ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
    ## 
    ##   set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
    ##   set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
    ## 
    ##   if {$raddr_width != $waddr_width} {
    ##     puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
    ##     set range 65536
    ##   } else {
    ##     if {$raddr_width >= 16} {
    ##       set range 65536
    ##     } else {
    ##       set range [expr 1 << $raddr_width]
    ##     }
    ##   }
    ## 
    ##   ipx::add_memory_map {s_axi} [ipx::current_core]
    ##   set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
    ##   ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
    ##   set_property range $range [ipx::get_address_blocks axi_lite \
    ##     -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
    ##   ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \
    ##     -of_objects [ipx::current_core]]
    ##   set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
    ##     -of_objects [ipx::get_bus_interfaces s_axi_aclk \
    ##     -of_objects [ipx::current_core]]]
    ##   ipx::save_core
    ## }
    ## proc adi_if_define {name} {
    ## 
    ##   ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
    ##   ipx::create_bus_definition analog.com interface $name 1.0
    ## 
    ##   set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
    ##   set_property xml_file_name ${name}.xml [ipx::current_busdef]
    ##   set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
    ## 
    ##   ipx::save_abstraction_definition [ipx::current_busabs]
    ##   ipx::save_bus_definition [ipx::current_busdef]
    ## }
    ## proc adi_if_ports {dir width name {type none}} {
    ## 
    ##   ipx::add_bus_abstraction_port $name [ipx::current_busabs]
    ##   set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
    ##   set_property master_presence required $m_intf
    ##   set_property slave_presence  required $m_intf
    ##   set_property master_width $width $m_intf
    ##   set_property slave_width  $width $m_intf
    ## 
    ##   set m_dir "in"
    ##   set s_dir "out"
    ##   if {$dir eq "output"} {
    ##     set m_dir "out"
    ##     set s_dir "in"
    ##   }
    ## 
    ##   set_property master_direction $m_dir $m_intf
    ##   set_property slave_direction  $s_dir $m_intf
    ## 
    ##   if {$type ne "none"} {
    ##     set_property is_${type} true $m_intf
    ##   }
    ## 
    ##   ipx::save_bus_definition [ipx::current_busdef]
    ##   ipx::save_abstraction_definition [ipx::current_busabs]
    ## }
    ## proc adi_if_infer_bus {if_name mode name maps} {
    ## 
    ##   ipx::add_bus_interface $name [ipx::current_core]
    ##   set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
    ##   set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
    ##   set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
    ##   set_property interface_mode $mode $m_bus_if
    ## 
    ##   foreach map $maps  {
    ##     set m_maps [regexp -all -inline {\S+} $map]
    ##     lassign $m_maps p_name p_map
    ##     ipx::add_port_map $p_name $m_bus_if
    ##     set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
    ##   }
    ## }
    # adi_ip_create axi_ad9361
    create_project: Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1458.082 ; gain = 0.000
    ## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
    ## set_msg_config -id {BD 41-1343} -new_severity WARNING
    ## set_msg_config -id {BD 41-1306} -new_severity WARNING
    ## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
    ## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
    ## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
    ## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
    ## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
    ## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library'.
    INFO: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'.)
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/VIVADO_2021_2_Installation/Vivado/2021.2/data/ip'.
    # adi_ip_files axi_ad9361 [list \
    #   "$ad_hdl_dir/library/common/ad_rst.v" \
    #   "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \
    #   "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \
    #   "$ad_hdl_dir/library/xilinx/common/ad_data_out.v" \
    #   "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \
    #   "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
    #   "$ad_hdl_dir/library/common/ad_pnmon.v" \
    #   "$ad_hdl_dir/library/common/ad_dds_sine.v" \
    #   "$ad_hdl_dir/library/common/ad_dds_1.v" \
    #   "$ad_hdl_dir/library/common/ad_dds.v" \
    #   "$ad_hdl_dir/library/common/ad_datafmt.v" \
    #   "$ad_hdl_dir/library/common/ad_iqcor.v" \
    #   "$ad_hdl_dir/library/common/ad_addsub.v" \
    #   "$ad_hdl_dir/library/common/ad_tdd_control.v" \
    #   "$ad_hdl_dir/library/common/ad_pps_receiver.v" \
    #   "$ad_hdl_dir/library/common/up_axi.v" \
    #   "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
    #   "$ad_hdl_dir/library/common/up_xfer_status.v" \
    #   "$ad_hdl_dir/library/common/up_clock_mon.v" \
    #   "$ad_hdl_dir/library/common/up_delay_cntrl.v" \
    #   "$ad_hdl_dir/library/common/up_adc_common.v" \
    #   "$ad_hdl_dir/library/common/up_adc_channel.v" \
    #   "$ad_hdl_dir/library/common/up_dac_common.v" \
    #   "$ad_hdl_dir/library/common/up_dac_channel.v" \
    #   "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \
    #   "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
    #   "$ad_hdl_dir/library/common/ad_pps_receiver_constr.ttcl" \
    #   "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
    #   "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
    #   "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
    #   "axi_ad9361_constr.xdc" \
    #   "xilinx/axi_ad9361_lvds_if.v" \
    #   "xilinx/axi_ad9361_cmos_if.v" \
    #   "axi_ad9361_rx_pnmon.v" \
    #   "axi_ad9361_rx_channel.v" \
    #   "axi_ad9361_rx.v" \
    #   "axi_ad9361_tx_channel.v" \
    #   "axi_ad9361_tx.v" \
    #   "axi_ad9361_tdd.v" \
    #   "axi_ad9361_tdd_if.v" \
    #   "axi_ad9361.v" ]
    # adi_ip_properties axi_ad9361
    WARNING: [IP_Flow 19-5226] Project source file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_pps_receiver_constr.ttcl' ignored by IP packager.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_addsub.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/xilinx/common/ad_data_clk.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/xilinx/common/ad_data_in.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/xilinx/common/ad_data_out.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_datafmt.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_dds.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_dds_1.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_dds_sine.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_iqcor.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/xilinx/common/ad_mul.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_pnmon.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_pps_receiver.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_rst.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_tdd_control.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_adc_channel.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_adc_common.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_axi.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_clock_mon.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_dac_channel.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_dac_common.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_delay_cntrl.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_tdd_cntrl.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_xfer_cntrl.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_xfer_status.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_addsub.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/xilinx/common/ad_data_clk.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/xilinx/common/ad_data_in.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/xilinx/common/ad_data_out.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_datafmt.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/xilinx/common/ad_dcfilter.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_dds.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_dds_1.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_dds_sine.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_iqcor.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/xilinx/common/ad_mul.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_pnmon.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_pps_receiver.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_rst.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/ad_tdd_control.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_adc_channel.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_adc_common.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_axi.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_clock_mon.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_dac_channel.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_dac_common.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_delay_cntrl.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_tdd_cntrl.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_xfer_cntrl.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/common/up_xfer_status.v' appears to be outside of the project area 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'rx_in'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'rx_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'rx_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'tx_out'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'tx_out_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'tx_out_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_i1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'dac_q1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_10' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_11' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_2' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_3' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_4' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_5' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_6' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_7' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_8' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_9' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_n_0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_n_1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_n_2' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_n_3' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_n_4' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_n_5' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_p_0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_p_1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_p_2' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_p_3' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_p_4' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'rx_in_p_5' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_10' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_11' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_2' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_3' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_4' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_5' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_6' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_7' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_8' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_9' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_n_0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_n_1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_n_2' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_n_3' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_n_4' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_n_5' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_p_0' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_p_1' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_p_2' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_p_3' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_p_4' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port VALID on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'tx_out_p_5' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'rx_in'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'rx_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'rx_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'tx_out'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'tx_out_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'tx_out_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i0_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_6' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_7' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_8' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_i1_9' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_0' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_1' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_10' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_11' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_12' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_13' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_14' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_15' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_2' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_3' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_4' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'adc_q0_5' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
    INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
    INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type master.
    WARNING: [IP_Flow 19-5463] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type master.
    INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'rx_in'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'rx_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'rx_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'tx_out'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'tx_out_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'tx_out_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'adc_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_i0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_i1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_q0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'dac_q1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'rx_in'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'rx_in_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'rx_in_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'tx_out'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'tx_out_n'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-5151] The Range '5:0' is present in all ports of the interface 'tx_out_p'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
    INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
    INFO: [IP_Flow 19-4728] Bus Interface 'gps_pps_irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
    INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
    INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-5905] All packaged files should be located below the IP definition file (xml)
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_i0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_i1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_q0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_data_q1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_0': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_1': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_10': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_11': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_2': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_3': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_4': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_5': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_6': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_7': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_8': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_9': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in_n' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_0': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in_n' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_1': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in_n' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_2': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in_n' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_3': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in_n' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_4': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in_n' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_n_5': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in_p' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_0': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in_p' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_1': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in_p' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_2': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in_p' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_3': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in_p' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_4': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'rx_data_in_p' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'rx_in_p_5': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_0': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_1': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_10': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_11': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_2': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_3': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_4': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_5': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_6': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_7': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_8': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_9': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_0': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_1': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_2': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_3': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_4': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_n_5': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_0': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_1': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_2': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_3': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_4': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tx_out_p_5': A port map to the required logical port "VALID" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_i1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q0' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'adc_data_q1' and definition port 'DATA'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'adc_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_i1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_in': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'dac_sync_out' and definition port 'SYNC'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_out': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q0_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_0': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_1': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_10': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_11': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_12': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_13': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_14': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_15': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_2': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_3': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_4': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_5': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_6': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_7': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_8': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac_q1_9': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tdd': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tdd': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'tdd_sync_cntr' and definition port 'SYNC'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tdd_cntr': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'tdd_cntr': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'up': A port map to the required logical port "CMD_WR_EN" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'up': A port map to the required logical port "CMD_WR_DATA" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'up': A port map to the required logical port "MEM_RESET" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'up': A port map to the required logical port "ENABLED" of the bus abstraction "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-5661] Bus Interface 'delay_clk' does not have any bus interfaces associated with it.
    WARNING: [IP_Flow 19-5661] Bus Interface 'l_clk' does not have any bus interfaces associated with it.
    WARNING: [IP_Flow 19-4751] Bus Interface 'l_clk': FREQ_HZ bus parameter is missing for output clock interface.
    WARNING: [IP_Flow 19-5661] Bus Interface 's_axi_aclk' does not have any bus interfaces associated with it.
    INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
    INFO: [IP_Flow 19-2187] The Product Guide file is missing.
    INFO: [IP_Flow 19-4623] Unrecognized family  azynquplus.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  azynquplus.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  qkintexu.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  qkintexu.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  qkintexuplus.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  qkintexuplus.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  qrkintexu.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  qrkintexu.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  qzynquplus.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  qzynquplus.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  qzynquplusRFSOC.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  qzynquplusRFSOC.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  versalaicore.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  versalaicore.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  versalprime.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  versalprime.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  zynquplusRFSOC.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  zynquplusRFSOC.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  zynquplusRFSOCes1.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  zynquplusRFSOCes1.  Please verify spelling and reissue command to set the supported files.
    WARNING: [Ipptcl 7-1550] All additional files should be added in a directory below the IP definition file (xml)
    WARNING: [IP_Flow 19-1971] File named "../xilinx/common/up_xfer_cntrl_constr.xdc" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    INFO: [Common 17-206] Exiting Vivado at Fri Sep 23 08:50:43 2022...
    ERROR: [Common 17-55] 'set_property' expects at least one object.
    Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
    adi_make::lib jesd204/jesd204_rx
    Building:
    - jesd204/jesd204_rx
    Please wait, this might take a few minutes
    - Done building jesd204/jesd204_common
    - Done building jesd204/interfaces
    - Done building jesd204/jesd204_rx
    adi_make::lib axi_dmac
    Building:
    - axi_dmac
    Please wait, this might take a few minutes
    - Done building util_cdc
    - Done building util_axis_fifo
    - Done building util_axis_resize
    - Done building axi_dmac
    source ./system_project.tcl
    # source ../../scripts/adi_env.tcl
    ## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
    ## set ad_phdl_dir $ad_hdl_dir
    ## if [info exists ::env(ADI_HDL_DIR)] {
    ##   set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
    ## }
    ## if [info exists ::env(ADI_PHDL_DIR)] {
    ##   set ad_phdl_dir [file normalize $::env(ADI_PHDL_DIR)]
    ## }
    # source $ad_hdl_dir/projects/scripts/adi_project.tcl
    ## variable p_board
    ## variable p_device
    ## variable sys_zynq
    ## variable p_prcfg_init
    ## variable p_prcfg_list
    ## variable p_prcfg_status
    ## if {![info exists REQUIRED_VIVADO_VERSION]} {
    ##   #set REQUIRED_VIVADO_VERSION "2017.4.1"
    ##   set REQUIRED_VIVADO_VERSION "2021.2"
    ## }
    ## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
    ##   set IGNORE_VERSION_CHECK 1
    ## } elseif {![info exists IGNORE_VERSION_CHECK]} {
    ##   set IGNORE_VERSION_CHECK 0
    ## }
    ## set p_board "not-applicable"
    ## set p_device "none"
    ## set sys_zynq 1
    ## set ADI_POWER_OPTIMIZATION 0
    ## proc adi_project_xilinx {project_name {mode 0}} {
    ## 
    ##   global ad_hdl_dir
    ##   global ad_phdl_dir
    ##   global p_board
    ##   global p_device
    ##   global sys_zynq
    ##   global REQUIRED_VIVADO_VERSION
    ##   global IGNORE_VERSION_CHECK
    ## 
    ##   if [regexp "_ac701$" $project_name] {
    ##     set p_device "xc7a200tfbg676-2"
    ##     set p_board "xilinx.com:ac701:part0:1.0"
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_kc705$" $project_name] {
    ##     set p_device "xc7k325tffg900-2"
    ##     set p_board "xilinx.com:kc705:part0:1.1"
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_vc707$" $project_name] {
    ##     set p_device "xc7vx485tffg1761-2"
    ##     set p_board "xilinx.com:vc707:part0:1.1"
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_kcu105$" $project_name] {
    ##     set p_device "xcku040-ffva1156-2-e"
    ##     set p_board "xilinx.com:kcu105:part0:1.1"
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_zed$" $project_name] {
    ##     set p_device "xc7z020clg484-1"
    ## 	# set p_board "avnet.com:zedboard:part0:1.4"
    ##     set p_board "em.avnet.com:zed:part0:1.3"
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_microzed$" $project_name] {
    ##     set p_device "xc7z010clg400-1"
    ##     set p_board "not-applicable"
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_zc702$" $project_name] {
    ##     set p_device "xc7z020clg484-1"
    ##     set p_board "xilinx.com:zc702:part0:1.2"
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_zc706$" $project_name] {
    ##     set p_device "xc7z045ffg900-2"
    ##     set p_board "xilinx.com:zc706:part0:1.2"
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_mitx045$" $project_name] {
    ##     set p_device "xc7z045ffg900-2"
    ##     set p_board "not-applicable"
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_zcu102$" $project_name] {
    ##     set p_device "xczu9eg-ffvb1156-2-e"
    ##     set p_board "xilinx.com:zcu102:part0:3.1"
    ##     set sys_zynq 2
    ##   }
    ## 
    ##   set VIVADO_VERSION [version -short]
    ##   if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
    ##     puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
    ##     puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
    ##     puts -nonewline "got $VIVADO_VERSION.\n"
    ##   }
    ## 
    ##   if {$mode == 0} {
    ##     set project_system_dir "./$project_name.srcs/sources_1/bd/system"
    ##     create_project $project_name . -part $p_device -force
    ##   } else {
    ##     set project_system_dir ".srcs/sources_1/bd/system"
    ##     create_project -in_memory -part $p_device
    ##   }
    ## 
    ##   if {$mode == 1} {
    ##     file mkdir $project_name.data
    ##   }
    ## 
    ##   if {$p_board ne "not-applicable"} {
    ##     set_property board_part $p_board [current_project]
    ##   }
    ## 
    ##   set lib_dirs $ad_hdl_dir/library
    ##   if {$ad_hdl_dir ne $ad_phdl_dir} {
    ##     lappend lib_dirs $ad_phdl_dir/library
    ##   }
    ## 
    ##   set_property ip_repo_paths $lib_dirs [current_fileset]
    ##   update_ip_catalog
    ## 
    ##   ## Load custom message severity definitions
    ##   source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
    ## 
    ##   create_bd_design "system"
    ##   source system_bd.tcl
    ## 
    ##   save_bd_design
    ##   validate_bd_design
    ## 
    ##   set_property synth_checkpoint_mode None [get_files  $project_system_dir/system.bd]
    ##   generate_target {synthesis implementation} [get_files  $project_system_dir/system.bd]
    ##   make_wrapper -files [get_files $project_system_dir/system.bd] -top
    ## 
    ##   if {$mode == 0} {
    ##     import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v
    ##   } else {
    ##     write_hwdef -file "$project_name.data/$project_name.hwdef"
    ##   }
    ## }
    ## proc adi_project_files {project_name project_files} {
    ## 
    ##   add_files -norecurse -fileset sources_1 $project_files
    ##   set_property top system_top [current_fileset]
    ## }
    ## proc adi_project_run {project_name} {
    ##   global ADI_POWER_OPTIMIZATION
    ## 
    ##   launch_runs synth_1
    ##   wait_on_run synth_1
    ##   open_run synth_1
    ##   report_timing_summary -file timing_synth.log
    ## 
    ##   if {![info exists ::env(ADI_NO_BITSTREAM_COMPRESSION)] && ![info exists ADI_NO_BITSTREAM_COMPRESSION]} {
    ##     set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
    ##   }
    ## 
    ##   if {$ADI_POWER_OPTIMIZATION == 1} {
    ##   set_property STEPS.POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
    ##   set_property STEPS.POST_PLACE_POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
    ##   }
    ## 
    ##   launch_runs impl_1 -to_step write_bitstream
    ##   wait_on_run impl_1
    ##   open_run impl_1
    ##   report_timing_summary -file timing_impl.log
    ## 
    ##   file mkdir $project_name.sdk
    ## 
    ##   if [expr [get_property SLACK [get_timing_paths]] < 0] {
    ##     file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top_bad_timing.hdf
    ##   } else {
    ##     file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top.hdf
    ##   }
    ## 
    ##   if [expr [get_property SLACK [get_timing_paths]] < 0] {
    ##     return -code error [format "ERROR: Timing Constraints NOT met!"]
    ##   }
    ## }
    ## proc adi_project_synth {project_name prcfg_name hdl_files {xdc_files ""}} {
    ## 
    ##   global p_device
    ## 
    ##   set p_prefix "$project_name.data/$project_name"
    ## 
    ##   if {$prcfg_name eq ""} {
    ## 
    ##     read_verilog .srcs/sources_1/bd/system/hdl/system_wrapper.v
    ##     read_verilog $hdl_files
    ##     read_xdc $xdc_files
    ## 
    ##     synth_design -mode default -top system_top -part $p_device > $p_prefix.synth.rds
    ##     write_checkpoint -force $p_prefix.synth.dcp
    ##     close_project
    ## 
    ##   } else {
    ## 
    ##     create_project -in_memory -part $p_device
    ##     read_verilog $hdl_files
    ##     synth_design -mode out_of_context -top "prcfg" -part $p_device > $p_prefix.${prcfg_name}_synth.rds
    ##     write_checkpoint -force $p_prefix.${prcfg_name}_synth.dcp
    ##     close_project
    ##   }
    ## }
    ## proc adi_project_impl {project_name prcfg_name {xdc_files ""}} {
    ## 
    ##   global p_device
    ##   global p_prcfg_init
    ##   global p_prcfg_list
    ##   global p_prcfg_status
    ## 
    ##   set p_prefix "$project_name.data/$project_name"
    ## 
    ##   if {$prcfg_name eq "default"} {
    ##     set p_prcfg_status 0
    ##     set p_prcfg_list ""
    ##     set p_prcfg_init "$p_prefix.${prcfg_name}_impl.dcp"
    ##     file mkdir $project_name.sdk
    ##   }
    ## 
    ##   if {$prcfg_name eq "default"} {
    ## 
    ##     open_checkpoint $p_prefix.synth.dcp -part $p_device
    ##     read_xdc $xdc_files
    ##     read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
    ##     set_property HD.RECONFIGURABLE 1 [get_cells i_prcfg]
    ##     opt_design > $p_prefix.${prcfg_name}_opt.rds
    ##     write_debug_probes -force $p_prefix.${prcfg_name}_debug_nets.ltx
    ##     place_design > $p_prefix.${prcfg_name}_place.rds
    ##     route_design > $p_prefix.${prcfg_name}_route.rds
    ## 
    ##   } else {
    ## 
    ##     open_checkpoint $p_prefix.default_impl_bb.dcp -part $p_device
    ##     lock_design -level routing
    ##     read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
    ##     read_xdc $xdc_files
    ##     opt_design > $p_prefix.${prcfg_name}_opt.rds
    ##     place_design > $p_prefix.${prcfg_name}_place.rds
    ##     route_design > $p_prefix.${prcfg_name}_route.rds
    ##   }
    ## 
    ##   write_checkpoint -force $p_prefix.${prcfg_name}_impl.dcp
    ##   report_utilization -pblocks pb_prcfg -file $p_prefix.${prcfg_name}_utilization.rpt
    ##   report_timing_summary -file $p_prefix.${prcfg_name}_timing_summary.rpt
    ## 
    ##   if [expr [get_property SLACK [get_timing_paths]] < 0] {
    ##     set p_prcfg_status 1
    ##     puts "CRITICAL WARNING: Timing Constraints NOT met ($prcfg_name)!"
    ##   }
    ## 
    ##   write_checkpoint -force -cell i_prcfg $p_prefix.${prcfg_name}_prcfg_impl.dcp
    ##   update_design -cell i_prcfg -black_box
    ##   write_checkpoint -force $p_prefix.${prcfg_name}_impl_bb.dcp
    ##   open_checkpoint $p_prefix.${prcfg_name}_impl.dcp -part $p_device
    ##   write_bitstream -force -bin_file -file $p_prefix.${prcfg_name}.bit
    ##   write_sysdef -hwdef $p_prefix.hwdef -bitfile $p_prefix.${prcfg_name}.bit -file $p_prefix.${prcfg_name}.hdf
    ##   file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.${prcfg_name}.hdf
    ## 
    ##   if {$prcfg_name ne "default"} {
    ##     lappend p_prcfg_list "$p_prefix.${prcfg_name}_impl.dcp"
    ##   }
    ## 
    ##   if {$prcfg_name eq "default"} {
    ##     file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.hdf
    ##   }
    ## }
    ## proc adi_project_verify {project_name} {
    ## 
    ##   global p_prcfg_init
    ##   global p_prcfg_list
    ##   global p_prcfg_status
    ## 
    ##   set p_prefix "$project_name.data/$project_name"
    ## 
    ##   pr_verify -full_check -initial $p_prcfg_init \
    ##     -additional $p_prcfg_list \
    ##     -file $p_prefix.prcfg_verify.log
    ## 
    ##   if {$p_prcfg_status == 1} {
    ##     return -code error [format "ERROR: Timing Constraints NOT met!"]
    ##   }
    ## }
    # source $ad_hdl_dir/projects/scripts/adi_board.tcl
    ## variable sys_cpu_interconnect_index
    ## variable sys_hp0_interconnect_index
    ## variable sys_hp1_interconnect_index
    ## variable sys_hp2_interconnect_index
    ## variable sys_hp3_interconnect_index
    ## variable sys_mem_interconnect_index
    ## variable xcvr_index
    ## variable xcvr_tx_index
    ## variable xcvr_rx_index
    ## variable xcvr_instance
    ## set sys_cpu_interconnect_index 0
    ## set sys_hp0_interconnect_index -1
    ## set sys_hp1_interconnect_index -1
    ## set sys_hp2_interconnect_index -1
    ## set sys_hp3_interconnect_index -1
    ## set sys_mem_interconnect_index -1
    ## set xcvr_index -1
    ## set xcvr_tx_index 0
    ## set xcvr_rx_index 0
    ## set xcvr_instance NONE
    ## proc ad_ip_instance {i_ip i_name} {
    ## 
    ##   create_bd_cell -type ip -vlnv [get_ipdefs -all -filter "VLNV =~ *:${i_ip}:* && \
    ##     design_tool_contexts =~ *IPI* && UPGRADE_VERSIONS == \"\""] ${i_name}
    ## }
    ## proc ad_ip_parameter {i_name i_param i_value} {
    ## 
    ##   set_property ${i_param} ${i_value} [get_bd_cells ${i_name}]
    ## }
    ## proc ad_connect_type {p_name} {
    ## 
    ##   set m_name ""
    ## 
    ##   if {$m_name eq ""} {set m_name [get_bd_intf_pins  -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_pins       -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_intf_ports -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_ports      -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_intf_nets  -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_nets       -quiet $p_name]}
    ## 
    ##   return $m_name
    ## }
    ## proc ad_connect {p_name_1 p_name_2} {
    ## 
    ##   if {($p_name_2 eq "GND") || ($p_name_2 eq "VCC")} {
    ##     set p_size 1
    ##     set p_msb [get_property left [get_bd_pins $p_name_1]]
    ##     set p_lsb [get_property right [get_bd_pins $p_name_1]]
    ##     if {($p_msb ne "") && ($p_lsb ne "")} {
    ##       set p_size [expr (($p_msb + 1) - $p_lsb)]
    ##     }
    ##     set p_cell_name [regsub -all {/} $p_name_1 "_"]
    ##     set p_cell_name "${p_cell_name}_${p_name_2}"
    ##     if {$p_name_2 eq "VCC"} {
    ##       set p_value -1
    ##     } else {
    ##       set p_value 0
    ##     }
    ##     ad_ip_instance xlconstant $p_cell_name
    ##     set_property CONFIG.CONST_WIDTH $p_size [get_bd_cells $p_cell_name]
    ##     set_property CONFIG.CONST_VAL $p_value [get_bd_cells $p_cell_name]
    ##     puts "connect_bd_net $p_cell_name/dout $p_name_1"
    ##     connect_bd_net [get_bd_pins $p_cell_name/dout] [get_bd_pins $p_name_1]
    ##     return
    ##   }
    ## 
    ##   set m_name_1 [ad_connect_type $p_name_1]
    ##   set m_name_2 [ad_connect_type $p_name_2]
    ## 
    ##   if {$m_name_1 eq ""} {
    ##     if {[get_property CLASS $m_name_2] eq "bd_intf_pin"} {
    ##       puts "create_bd_intf_net $p_name_1"
    ##       create_bd_intf_net $p_name_1
    ##     }
    ##     if {[get_property CLASS $m_name_2] eq "bd_pin"} {
    ##       puts "create_bd_net $p_name_1"
    ##       create_bd_net $p_name_1
    ##     }
    ##     set m_name_1 [ad_connect_type $p_name_1]
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} {
    ##     puts "connect_bd_intf_net $m_name_1 $m_name_2"
    ##     connect_bd_intf_net $m_name_1 $m_name_2
    ##     return
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_pin"} {
    ##     puts "connect_bd_net $m_name_1 $m_name_2"
    ##     connect_bd_net $m_name_1 $m_name_2
    ##     return
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_net"} {
    ##     puts "connect_bd_net -net $m_name_1 $m_name_2"
    ##     connect_bd_net -net $m_name_1 $m_name_2
    ##     return
    ##   }
    ## }
    ## proc ad_disconnect {p_name_1 p_name_2} {
    ## 
    ##   set m_name_1 [ad_connect_type $p_name_1]
    ##   set m_name_2 [ad_connect_type $p_name_2]
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_net"} {
    ##     disconnect_bd_net $m_name_1 $m_name_2
    ##     return
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_port"} {
    ##     delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
    ##       [find_bd_objs -relation connected_to $m_name_1]]
    ##     delete_bd_objs -quiet $m_name_1
    ##     return
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_pin"} {
    ##     delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
    ##       [find_bd_objs -relation connected_to $m_name_1]]
    ##     delete_bd_objs -quiet $m_name_1
    ##     return
    ##   }
    ## }
    ## proc ad_reconct {p_name_1 p_name_2} {
    ## 
    ##   set m_name_1 [ad_connect_type $p_name_1]
    ##   set m_name_2 [ad_connect_type $p_name_2]
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_pin"} {
    ##     delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
    ##       [find_bd_objs -relation connected_to $m_name_1]]
    ##     delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
    ##       [find_bd_objs -relation connected_to $m_name_2]]
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} {
    ##     delete_bd_objs -quiet [get_bd_intf_nets -quiet -of_objects \
    ##       [find_bd_objs -relation connected_to $m_name_1]]
    ##     delete_bd_objs -quiet [get_bd_intf_nets -quiet -of_objects \
    ##       [find_bd_objs -relation connected_to $m_name_2]]
    ##   }
    ## 
    ##   ad_connect $p_name_1 $p_name_2
    ## }
    ## proc ad_xcvrcon {u_xcvr a_xcvr a_jesd {lane_map {}}} {
    ##   
    ##   global xcvr_index
    ##   global xcvr_tx_index
    ##   global xcvr_rx_index
    ##   global xcvr_instance
    ## 
    ##   set no_of_lanes [get_property CONFIG.NUM_OF_LANES [get_bd_cells $a_xcvr]]
    ##   set qpll_enable [get_property CONFIG.QPLL_ENABLE [get_bd_cells $a_xcvr]]
    ##   set tx_or_rx_n [get_property CONFIG.TX_OR_RX_N [get_bd_cells $a_xcvr]]
    ## 
    ## #  set jesd204_vlnv [get_property VLNV $a_jesd]
    ## #
    ## #  if {[string first "analog.com" $jesd204_vlnv] == 0} {
    ## #    set jesd204_type 0
    ## #  } elseif {[string first "xilinx.com" $jesd204_vlnv] == 0} {
    ## #    set jesd204_type 1
    ## #  } else {
    ## #    return -code 1 "Unsupported JESD204 core type."
    ## #  }
    ## 
    ##   set jesd204_bd_type [get_property TYPE [get_bd_cells $a_jesd]]
    ## 
    ##   if {$jesd204_bd_type == "hier"} {
    ##     set jesd204_type 0
    ##   } else {
    ##     set jesd204_type 1
    ##   }
    ## 
    ##   if {$xcvr_instance ne $u_xcvr} {
    ##     set xcvr_index [expr ($xcvr_index + 1)]
    ##     set xcvr_tx_index 0
    ##     set xcvr_rx_index 0
    ##     set xcvr_instance $u_xcvr
    ##   }
    ## 
    ##   set txrx "rx"
    ##   set data_dir "I"
    ##   set ctrl_dir "O"
    ##   set index $xcvr_rx_index
    ## 
    ##   if {$tx_or_rx_n == 1} {
    ## 
    ##     set txrx "tx"
    ##     set data_dir "O"
    ##     set ctrl_dir "I"
    ##     set index $xcvr_tx_index
    ##   }
    ## 
    ##   set m_sysref ${txrx}_sysref_${index}
    ##   set m_sync ${txrx}_sync_${index}
    ##   set m_data ${txrx}_data
    ## 
    ##   if {$xcvr_index >= 1} {
    ## 
    ##     set m_sysref ${txrx}_sysref_${xcvr_index}_${index}
    ##     set m_sync ${txrx}_sync_${xcvr_index}_${index}
    ##     set m_data ${txrx}_data_${xcvr_index}
    ##   }
    ## 
    ##   create_bd_port -dir I $m_sysref
    ##   create_bd_port -dir ${ctrl_dir} $m_sync
    ##   ad_ip_instance proc_sys_reset ${a_jesd}_rstgen
    ## 
    ##   for {set n 0} {$n < $no_of_lanes} {incr n} {
    ## 
    ##     set m [expr ($n + $index)]
    ## 
    ##     if {$tx_or_rx_n == 0} {
    ##       ad_connect  ${a_xcvr}/up_es_${n} ${u_xcvr}/up_es_${m}
    ##       if {$jesd204_type == 0} {
    ##         ad_connect  ${a_jesd}/phy_en_char_align ${u_xcvr}/${txrx}_calign_${m}
    ##       } else {
    ##         ad_connect  ${a_jesd}/rxencommaalign_out ${u_xcvr}/${txrx}_calign_${m}
    ##       }
    ##     }
    ## 
    ##     if {(($m%4) == 0) && ($qpll_enable == 1)} {
    ##       ad_connect  ${a_xcvr}/up_cm_${n} ${u_xcvr}/up_cm_${m}
    ##     }
    ## 
    ##     if {$lane_map != {}} {
    ##       set phys_lane [expr [lindex $lane_map $n] + $index]
    ##     } else {
    ##       set phys_lane $m
    ##     }
    ## 
    ##     ad_connect  ${a_xcvr}/up_ch_${n} ${u_xcvr}/up_${txrx}_${m}
    ##     ad_connect  ${u_xcvr}/${txrx}_out_clk_${index} ${u_xcvr}/${txrx}_clk_${m}
    ##     if {$jesd204_type == 0} {
    ##       ad_connect  ${u_xcvr}/${txrx}_${phys_lane} ${a_jesd}/${txrx}_phy${n}
    ##     } else {
    ##       ad_connect  ${u_xcvr}/${txrx}_${phys_lane} ${a_jesd}/gt${n}_${txrx}
    ##     }
    ## 
    ##     create_bd_port -dir ${data_dir} ${m_data}_${m}_p
    ##     create_bd_port -dir ${data_dir} ${m_data}_${m}_n
    ##     ad_connect  ${u_xcvr}/${txrx}_${m}_p ${m_data}_${m}_p
    ##     ad_connect  ${u_xcvr}/${txrx}_${m}_n ${m_data}_${m}_n
    ##   }
    ## 
    ##   if {$jesd204_type == 0} {
    ##     ad_connect  ${a_jesd}/sysref $m_sysref
    ##     ad_connect  ${a_jesd}/sync $m_sync
    ##     ad_connect  ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}/device_clk
    ## #    if {$tx_or_rx_n == 0} {
    ## #      ad_connect  ${a_xcvr}/up_status ${a_jesd}/phy_ready
    ## #    }
    ##   } else {
    ##     ad_connect  ${a_jesd}/${txrx}_sysref $m_sysref
    ##     ad_connect  ${a_jesd}/${txrx}_sync $m_sync
    ##     ad_connect  ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}/${txrx}_core_clk
    ##     ad_connect  ${a_xcvr}/up_status ${a_jesd}/${txrx}_reset_done
    ##     ad_connect  ${a_jesd}_rstgen/peripheral_reset ${a_jesd}/${txrx}_reset
    ##   }
    ## 
    ##   ad_connect  ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}_rstgen/slowest_sync_clk
    ##   ad_connect  sys_cpu_resetn ${a_jesd}_rstgen/ext_reset_in
    ## 
    ##   if {$tx_or_rx_n == 0} {
    ##     set xcvr_rx_index [expr ($xcvr_rx_index + $no_of_lanes)]
    ##   }
    ## 
    ##   if {$tx_or_rx_n == 1} {
    ##     set xcvr_tx_index [expr ($xcvr_tx_index + $no_of_lanes)]
    ##   }
    ## }
    ## proc ad_xcvrpll {m_src m_dst} {
    ## 
    ##   foreach p_dst [get_bd_pins -quiet $m_dst] {
    ##     connect_bd_net [ad_connect_type $m_src] $p_dst
    ##   }
    ## }
    ## proc ad_mem_hp0_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP0")} {return}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp1_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP1")} {return}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp2_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP2")} {return}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp3_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP3")} {return}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
    ## }
    ## proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
    ## 
    ##   global sys_zynq
    ##   global sys_ddr_addr_seg
    ##   global sys_hp0_interconnect_index
    ##   global sys_hp1_interconnect_index
    ##   global sys_hp2_interconnect_index
    ##   global sys_hp3_interconnect_index
    ##   global sys_mem_interconnect_index
    ## 
    ##   set p_name_int $p_name
    ##   set p_clk_source [get_bd_pins -filter {DIR == O} -of_objects [get_bd_nets $p_clk]]
    ## 
    ##   if {$p_sel eq "MEM"} {
    ##     if {$sys_mem_interconnect_index < 0} {
    ##       ad_ip_instance axi_interconnect axi_mem_interconnect
    ##     }
    ##     set m_interconnect_index $sys_mem_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_mem_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs -of_objects [get_bd_cells axi_ddr_cntrl]]
    ##   }
    ## 
    ##   if {($p_sel eq "HP0") && ($sys_zynq == 1)} {
    ##     if {$sys_hp0_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP0
    ##       set_property CONFIG.PCW_USE_S_AXI_HP0 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance axi_interconnect axi_hp0_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp0_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP1") && ($sys_zynq == 1)} {
    ##     if {$sys_hp1_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP1
    ##       set_property CONFIG.PCW_USE_S_AXI_HP1 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance axi_interconnect axi_hp1_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp1_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP2") && ($sys_zynq == 1)} {
    ##     if {$sys_hp2_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP2
    ##       set_property CONFIG.PCW_USE_S_AXI_HP2 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance axi_interconnect axi_hp2_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp2_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP3") && ($sys_zynq == 1)} {
    ##     if {$sys_hp3_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP3
    ##       set_property CONFIG.PCW_USE_S_AXI_HP3 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance axi_interconnect axi_hp3_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp3_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP0") && ($sys_zynq == 2)} {
    ##     if {$sys_hp0_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP0_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP2 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance axi_interconnect axi_hp0_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp0_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/S_AXI_HP0_FPD/PLLPD_DDR_LOW]
    ##   }
    ## 
    ##   if {($p_sel eq "HP1") && ($sys_zynq == 2)} {
    ##     if {$sys_hp1_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP1_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP3 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance axi_interconnect axi_hp1_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp1_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/S_AXI_HP1_FPD/HP0_DDR_LOW]
    ##   }
    ## 
    ##   if {($p_sel eq "HP2") && ($sys_zynq == 2)} {
    ##     if {$sys_hp2_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP2_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP4 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance axi_interconnect axi_hp2_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp2_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/S_AXI_HP2_FPD/HP1_DDR_LOW]
    ##   }
    ## 
    ##   if {($p_sel eq "HP3") && ($sys_zynq == 2)} {
    ##     if {$sys_hp3_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP3_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP5 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance axi_interconnect axi_hp3_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp3_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/S_AXI_HP3_FPD/HP2_DDR_LOW]
    ##   }
    ## 
    ##   set i_str "S$m_interconnect_index"
    ##   if {$m_interconnect_index < 10} {
    ##     set i_str "S0$m_interconnect_index"
    ##   }
    ## 
    ##   set m_interconnect_index [expr $m_interconnect_index + 1]
    ## 
    ##   set p_intf_name [lrange [split $p_name_int "/"] end end]
    ##   set p_cell_name [lrange [split $p_name_int "/"] 0 0]
    ##   set p_intf_clock [get_bd_pins -filter "TYPE == clk && (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
    ##     CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
    ##     CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" -quiet -of_objects [get_bd_cells $p_cell_name]]
    ##   if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne "" ||
    ##       $p_intf_clock eq $p_clk_source} {
    ##     set p_intf_clock ""
    ##   }
    ## 
    ##   regsub clk $p_clk resetn p_rst
    ##   if {[get_bd_nets -quiet $p_rst] eq ""} {
    ##     set p_rst sys_cpu_resetn
    ##   }
    ## 
    ##   if {$m_interconnect_index == 0} {
    ##     set_property CONFIG.NUM_MI 1 $m_interconnect_cell
    ##     set_property CONFIG.NUM_SI 1 $m_interconnect_cell
    ##     ad_connect $p_rst $m_interconnect_cell/ARESETN
    ##     ad_connect $p_clk $m_interconnect_cell/ACLK
    ##     ad_connect $p_rst $m_interconnect_cell/M00_ARESETN
    ##     ad_connect $p_clk $m_interconnect_cell/M00_ACLK
    ##     ad_connect $m_interconnect_cell/M00_AXI $p_name_int
    ##     if {$p_intf_clock ne ""} {
    ##       ad_connect $p_clk $p_intf_clock
    ##     }
    ##   } else {
    ##     set_property CONFIG.NUM_SI $m_interconnect_index $m_interconnect_cell
    ##     ad_connect $p_rst $m_interconnect_cell/${i_str}_ARESETN
    ##     ad_connect $p_clk $m_interconnect_cell/${i_str}_ACLK
    ##     ad_connect $m_interconnect_cell/${i_str}_AXI $p_name_int
    ##     if {$p_intf_clock ne ""} {
    ##       ad_connect $p_clk $p_intf_clock
    ##     }
    ##     assign_bd_address $m_addr_seg
    ##   }
    ## 
    ##   if {$m_interconnect_index > 1} {
    ##     set_property CONFIG.STRATEGY {2} $m_interconnect_cell
    ##   }
    ## 
    ##   if {$p_sel eq "MEM"} {set sys_mem_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP0"} {set sys_hp0_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP1"} {set sys_hp1_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP2"} {set sys_hp2_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP3"} {set sys_hp3_interconnect_index $m_interconnect_index}
    ## 
    ## }
    ## proc ad_cpu_interconnect {p_address p_name} {
    ## 
    ##   global sys_zynq
    ##   global sys_cpu_interconnect_index
    ## 
    ##   set i_str "M$sys_cpu_interconnect_index"
    ##   if {$sys_cpu_interconnect_index < 10} {
    ##     set i_str "M0$sys_cpu_interconnect_index"
    ##   }
    ## 
    ##   if {$sys_cpu_interconnect_index == 0} {
    ##     ad_ip_instance axi_interconnect axi_cpu_interconnect
    ##     if {$sys_zynq == 2} {
    ##       ad_connect sys_cpu_clk sys_ps8/maxihpm0_lpd_aclk
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
    ##       ad_connect axi_cpu_interconnect/S00_AXI sys_ps8/M_AXI_HPM0_LPD
    ##     }
    ##     if {$sys_zynq == 1} {
    ##       ad_connect sys_cpu_clk sys_ps7/M_AXI_GP0_ACLK
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
    ##       ad_connect axi_cpu_interconnect/S00_AXI sys_ps7/M_AXI_GP0
    ##     }
    ##     if {$sys_zynq == 0} {
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
    ##       ad_connect axi_cpu_interconnect/S00_AXI sys_mb/M_AXI_DP
    ##     }
    ##   }
    ## 
    ##   if {$sys_zynq == 2} {
    ##     set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps8/Data]
    ##   }
    ##   if {$sys_zynq == 1} {
    ##     set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps7/Data]
    ##   }
    ##   if {$sys_zynq == 0} {
    ##     set sys_addr_cntrl_space [get_bd_addr_spaces sys_mb/Data]
    ##   }
    ## 
    ##   set sys_cpu_interconnect_index [expr $sys_cpu_interconnect_index + 1]
    ## 
    ## 
    ##   set p_cell [get_bd_cells $p_name]
    ##   set p_intf [get_bd_intf_pins -filter "MODE == Slave && VLNV == xilinx.com:interface:aximm_rtl:1.0"\
    ##     -of_objects $p_cell]
    ## 
    ##   set p_hier_cell $p_cell
    ##   set p_hier_intf $p_intf
    ## 
    ##   while {$p_hier_intf != "" && [get_property TYPE $p_hier_cell] == "hier"} {
    ##     set p_hier_intf [find_bd_objs -boundary_type lower \
    ##       -relation connected_to $p_hier_intf]
    ##     if {$p_hier_intf != {}} {
    ##       set p_hier_cell [get_bd_cells -of_objects $p_hier_intf]
    ##     } else {
    ##       set p_hier_cell {}
    ##     }
    ##   }
    ## 
    ##   set p_intf_clock ""
    ##   set p_intf_reset ""
    ## 
    ##   if {$p_hier_cell != {}} {
    ##     set p_intf_name [lrange [split $p_hier_intf "/"] end end]
    ## 
    ##     set p_intf_clock [get_bd_pins -filter "TYPE == clk && \
    ##       (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
    ##       CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || \
    ##       CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
    ##       CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" \
    ##       -quiet -of_objects $p_hier_cell]
    ##     set p_intf_reset [get_bd_pins -filter "TYPE == rst && \
    ##       (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
    ##        CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* ||
    ##        CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
    ##        CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" \
    ##        -quiet -of_objects $p_hier_cell]
    ## 
    ##     if {($p_intf_clock ne "") && ($p_intf_reset eq "")} {
    ##       set p_intf_reset [get_property CONFIG.ASSOCIATED_RESET [get_bd_pins ${p_intf_clock}]]
    ##       if {$p_intf_reset ne ""} {
    ##         set p_intf_reset [get_bd_pins -filter "NAME == $p_intf_reset" -of_objects $p_hier_cell]
    ##       }
    ##     }
    ## 
    ##     # Trace back up
    ##     set p_hier_cell2 $p_hier_cell
    ## 
    ##     while {$p_intf_clock != {} && $p_hier_cell2 != $p_cell && $p_hier_cell2 != {}} {
    ##       puts $p_intf_clock
    ##       puts $p_hier_cell2
    ##       set p_intf_clock [find_bd_objs -boundary_type upper \
    ##         -relation connected_to $p_intf_clock]
    ##       if {$p_intf_clock != {}} {
    ##         set p_intf_clock [get_bd_pins [get_property PATH $p_intf_clock]]
    ##         set p_hier_cell2 [get_bd_cells -of_objects $p_intf_clock]
    ##       }
    ##     }
    ## 
    ##     set p_hier_cell2 $p_hier_cell
    ## 
    ##     while {$p_intf_reset != {} && $p_hier_cell2 != $p_cell && $p_hier_cell2 != {}} {
    ##       set p_intf_reset [find_bd_objs -boundary_type upper \
    ##         -relation connected_to $p_intf_reset]
    ##       if {$p_intf_reset != {}} {
    ##         set p_intf_reset [get_bd_pins [get_property PATH $p_intf_reset]]
    ##         set p_hier_cell2 [get_bd_cells -of_objects $p_intf_reset]
    ##       }
    ##     }
    ##   }
    ## 
    ## 
    ##   if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne ""} {
    ##     set p_intf_clock ""
    ##   }
    ##   if {$p_intf_reset ne ""} {
    ##     if {[find_bd_objs -quiet -relation connected_to $p_intf_reset] ne ""} {
    ##       set p_intf_reset ""
    ##     }
    ##   }
    ## 
    ##   set_property CONFIG.NUM_MI $sys_cpu_interconnect_index [get_bd_cells axi_cpu_interconnect]
    ## 
    ##   ad_connect sys_cpu_clk axi_cpu_interconnect/${i_str}_ACLK
    ##   if {$p_intf_clock ne ""} {
    ##     ad_connect sys_cpu_clk ${p_intf_clock}
    ##   }
    ##   ad_connect sys_cpu_resetn axi_cpu_interconnect/${i_str}_ARESETN
    ##   if {$p_intf_reset ne ""} {
    ##     ad_connect sys_cpu_resetn ${p_intf_reset}
    ##   }
    ##   ad_connect axi_cpu_interconnect/${i_str}_AXI ${p_intf}
    ## 
    ##   set p_seg [get_bd_addr_segs -of_objects $p_hier_cell]
    ##   set p_index 0
    ##   foreach p_seg_name $p_seg {
    ##     if {$p_index == 0} {
    ##       set p_seg_range [get_property range $p_seg_name]
    ##       if {$p_seg_range < 0x1000} {
    ##         set p_seg_range 0x1000
    ##       }
    ##       if {$sys_zynq == 2} {
    ##         if {($p_address >= 0x40000000) && ($p_address <= 0x4fffffff)} {
    ##           set p_address [expr ($p_address + 0x40000000)]
    ##         }
    ##         if {($p_address >= 0x70000000) && ($p_address <= 0x7fffffff)} {
    ##           set p_address [expr ($p_address + 0x20000000)]
    ##         }
    ##       }
    ##       create_bd_addr_seg -range $p_seg_range \
    ##         -offset $p_address $sys_addr_cntrl_space \
    ##         $p_seg_name "SEG_data_${p_name}"
    ##     } else {
    ##       assign_bd_address $p_seg_name
    ##     }
    ##     incr p_index
    ##   }
    ## }
    ## proc ad_cpu_interrupt {p_ps_index p_mb_index p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {$sys_zynq == 0} {set p_index_int $p_mb_index}
    ##   if {$sys_zynq >= 1} {set p_index_int $p_ps_index}
    ## 
    ##   set p_index [regsub -all {[^0-9]} $p_index_int ""]
    ##   set m_index [expr ($p_index - 8)]
    ## 
    ##   if {($sys_zynq == 2) && ($p_index <= 7)} {
    ##     set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_0/In$p_index]]
    ##     set p_pin [find_bd_objs -relation connected_to [get_bd_pins sys_concat_intc_0/In$p_index]]
    ## 
    ##     puts "delete_bd_objs $p_net $p_pin"
    ##     delete_bd_objs $p_net $p_pin
    ##     ad_connect sys_concat_intc_0/In$p_index $p_name
    ##   }
    ## 
    ##   if {($sys_zynq == 2) && ($p_index >= 8)} {
    ##     set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_1/In$m_index]]
    ##     set p_pin [find_bd_objs -relation connected_to [get_bd_pins sys_concat_intc_1/In$m_index]]
    ## 
    ##     puts "delete_bd_objs $p_net $p_pin"
    ##     delete_bd_objs $p_net $p_pin
    ##     ad_connect sys_concat_intc_1/In$m_index $p_name
    ##   }
    ## 
    ##   if {$sys_zynq <= 1} {
    ## 
    ##     set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc/In$p_index]]
    ##     set p_pin [find_bd_objs -relation connected_to [get_bd_pins sys_concat_intc/In$p_index]]
    ## 
    ##     puts "delete_bd_objs $p_net $p_pin"
    ##     delete_bd_objs $p_net $p_pin
    ##     ad_connect sys_concat_intc/In$p_index $p_name
    ##   }
    ## }
    # set p_device "xc7z035ifbg676-2L"
    # adi_project_xilinx adrv9361z7035_ccfmc_lvds
    INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
    Current project path is 'D:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/projects/adrv9361z7035/ccfmc_lvds_me'
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1704] No user IP repositories specified
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/VIVADO_2021_2_Installation/Vivado/2021.2/data/ip'.
    create_project: Time (s): cpu = 00:00:15 ; elapsed = 00:00:05 . Memory (MB): peak = 1424.309 ; gain = 0.000
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/library'.
    ## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
    ## set_msg_config -id {BD 41-1343} -new_severity WARNING
    ## set_msg_config -id {BD 41-1306} -new_severity WARNING
    ## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
    ## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
    ## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
    ## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
    ## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
    ## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
    Wrote  : <D:\VIVADO_2021_2_Partial_Reconfiguration\comms2_pr\projects\adrv9361z7035\ccfmc_lvds_me\adrv9361z7035_ccfmc_lvds.srcs\sources_1\bd\system\system.bd> 
    INFO: [BD 41-2613] The output directory d:/VIVADO_2021_2_Partial_Reconfiguration/comms2_pr/projects/adrv9361z7035/ccfmc_lvds_me/adrv9361z7035_ccfmc_lvds.gen/sources_1/bd/system for system cannot be found.
    create_bd_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1424.309 ; gain = 0.000
    ## source ../common/adrv9361z7035_bd.tcl
    ### create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
    ### create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
    ### create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
    ### create_bd_port -dir O spi0_csn_2_o
    ### create_bd_port -dir O spi0_csn_1_o
    ### create_bd_port -dir O spi0_csn_0_o
    ### create_bd_port -dir I spi0_csn_i
    ### create_bd_port -dir I spi0_clk_i
    ### create_bd_port -dir O spi0_clk_o
    ### create_bd_port -dir I spi0_sdo_i
    ### create_bd_port -dir O spi0_sdo_o
    ### create_bd_port -dir I spi0_sdi_i
    ### create_bd_port -dir O spi1_csn_2_o
    ### create_bd_port -dir O spi1_csn_1_o
    ### create_bd_port -dir O spi1_csn_0_o
    ### create_bd_port -dir I spi1_csn_i
    ### create_bd_port -dir I spi1_clk_i
    ### create_bd_port -dir O spi1_clk_o
    ### create_bd_port -dir I spi1_sdo_i
    ### create_bd_port -dir O spi1_sdo_o
    ### create_bd_port -dir I spi1_sdi_i
    ### create_bd_port -dir I -from 63 -to 0 gpio_i
    ### create_bd_port -dir O -from 63 -to 0 gpio_o
    ### create_bd_port -dir O -from 63 -to 0 gpio_t
    ### set otg_vbusoc      [create_bd_port -dir I otg_vbusoc]
    ### create_bd_port -dir I -type intr ps_intr_00
    ### create_bd_port -dir I -type intr ps_intr_01
    ### create_bd_port -dir I -type intr ps_intr_02
    ### create_bd_port -dir I -type intr ps_intr_03
    ### create_bd_port -dir I -type intr ps_intr_04
    ### create_bd_port -dir I -type intr ps_intr_05
    ### create_bd_port -dir I -type intr ps_intr_06
    ### create_bd_port -dir I -type intr ps_intr_07
    ### create_bd_port -dir I -type intr ps_intr_08
    ### create_bd_port -dir I -type intr ps_intr_09
    ### create_bd_port -dir I -type intr ps_intr_10
    ### create_bd_port -dir I -type intr ps_intr_11
    ### create_bd_port -dir I -type intr ps_intr_12
    ### create_bd_port -dir I -type intr ps_intr_13
    ### create_bd_port -dir I -type intr ps_intr_15
    ### ad_ip_instance processing_system7 sys_ps7
    create_bd_cell: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1424.309 ; gain = 0.000
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK0_VOLTAGE "LVCMOS 1.8V"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK1_VOLTAGE "LVCMOS 1.8V"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_PACKAGE_NAME fbg676
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_PERIPHERAL_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_ENET0_IO "MIO 16 .. 27"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_IO "MIO 52 .. 53"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_PERIPHERAL_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET_RESET_SELECT "Separate reset pins"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_RESET_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_RESET_IO "MIO 8"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_RESET_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_RESET_IO "MIO 51"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_PERIPHERAL_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_CD_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_CD_IO "MIO 50"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ 50
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_PERIPHERAL_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_PERIPHERAL_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_IO "MIO 7"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_PERIPHERAL_ENABLE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_PARTNO "MT41K256M16 RE-125"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH "32 Bit"
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF 0
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE 1
    WARNING: [#UNDEF] ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 -0.053
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [#UNDEF] ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 -0.059
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [#UNDEF] ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 0.065
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [#UNDEF] ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 0.066
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 0.264
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 0.265
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 0.330
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 0.330
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE 0
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK1_PORT 1
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST1_PORT 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK2_PORT 1
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST2_PORT 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 200.0
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 200.0
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR 1
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE 1
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 64
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_MODE REVERSE
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_PERIPHERAL_ENABLE 1
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_SPI0_IO EMIO
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE 1
    WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.053 . PS DDR interfaces might fail when entering negative DQS skew values. 
    WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.059 . PS DDR interfaces might fail when entering negative DQS skew values. 
    ### ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_SPI1_IO EMIO
    ### ad_ip_instance axi_iic axi_iic_main
    ### ad_ip_parameter axi_iic_main CONFIG.USE_BOARD_FLOW true
    ### ad_ip_parameter axi_iic_main CONFIG.IIC_BOARD_INTERFACE Custom
    ### ad_ip_instance xlconcat sys_concat_intc
    ### ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16
    ### ad_ip_instance proc_sys_reset sys_rstgen
    ### ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
    ### ad_ip_instance util_vector_logic sys_logic_inv
    ### ad_ip_parameter sys_logic_inv CONFIG.C_SIZE 1
    ### ad_ip_parameter sys_logic_inv CONFIG.C_OPERATION not
    ### ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0
    create_bd_net sys_cpu_clk
    connect_bd_net -net /sys_cpu_clk /sys_ps7/FCLK_CLK0
    ### ad_connect sys_200m_clk sys_ps7/FCLK_CLK1
    create_bd_net sys_200m_clk
    connect_bd_net -net /sys_200m_clk /sys_ps7/FCLK_CLK1
    ### ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
    create_bd_net sys_cpu_reset
    connect_bd_net -net /sys_cpu_reset /sys_rstgen/peripheral_reset
    ### ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
    create_bd_net sys_cpu_resetn
    connect_bd_net -net /sys_cpu_resetn /sys_rstgen/peripheral_aresetn
    ### ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
    connect_bd_net -net /sys_cpu_clk /sys_rstgen/slowest_sync_clk
    ### ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
    connect_bd_net /sys_rstgen/ext_reset_in /sys_ps7/FCLK_RESET0_N
    ### ad_connect ddr sys_ps7/DDR
    connect_bd_intf_net /ddr /sys_ps7/DDR
    ### ad_connect gpio_i sys_ps7/GPIO_I
    connect_bd_net /gpio_i /sys_ps7/GPIO_I
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/GPIO_I> is being overridden by the user with net <gpio_i_1>. This pin will not be connected as a part of interface connection <GPIO_0>.
    ### ad_connect gpio_o sys_ps7/GPIO_O
    connect_bd_net /gpio_o /sys_ps7/GPIO_O
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/GPIO_O> is being overridden by the user with net <sys_ps7_GPIO_O>. This pin will not be connected as a part of interface connection <GPIO_0>.
    ### ad_connect gpio_t sys_ps7/GPIO_T
    connect_bd_net /gpio_t /sys_ps7/GPIO_T
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/GPIO_T> is being overridden by the user with net <sys_ps7_GPIO_T>. This pin will not be connected as a part of interface connection <GPIO_0>.
    ### ad_connect fixed_io sys_ps7/FIXED_IO
    connect_bd_intf_net /fixed_io /sys_ps7/FIXED_IO
    ### ad_connect iic_main axi_iic_main/iic
    connect_bd_intf_net /iic_main /axi_iic_main/IIC
    ### ad_connect sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT
    connect_bd_net /sys_logic_inv/Res /sys_ps7/USB0_VBUS_PWRFAULT
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/USB0_VBUS_PWRFAULT> is being overridden by the user with net <sys_logic_inv_Res>. This pin will not be connected as a part of interface connection <USBIND_0>.
    ### ad_connect sys_logic_inv/Op1 otg_vbusoc
    connect_bd_net /sys_logic_inv/Op1 /otg_vbusoc
    ### ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O
    connect_bd_net /spi0_csn_2_o /sys_ps7/SPI0_SS2_O
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/SPI0_SS2_O> is being overridden by the user with net <sys_ps7_SPI0_SS2_O>. This pin will not be connected as a part of interface connection <SPI_0>.
    ### ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O
    connect_bd_net /spi0_csn_1_o /sys_ps7/SPI0_SS1_O
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/SPI0_SS1_O> is being overridden by the user with net <sys_ps7_SPI0_SS1_O>. This pin will not be connected as a part of interface connection <SPI_0>.
    ### ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O
    connect_bd_net /spi0_csn_0_o /sys_ps7/SPI0_SS_O
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/SPI0_SS_O> is being overridden by the user with net <sys_ps7_SPI0_SS_O>. This pin will not be connected as a part of interface connection <SPI_0>.
    ### ad_connect spi0_csn_i sys_ps7/SPI0_SS_I
    connect_bd_net /spi0_csn_i /sys_ps7/SPI0_SS_I
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/SPI0_SS_I> is being overridden by the user with net <spi0_csn_i_1>. This pin will not be connected as a part of interface connection <SPI_0>.
    ### ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I
    connect_bd_net /spi0_clk_i /sys_ps7/SPI0_SCLK_I
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/SPI0_SCLK_I> is being overridden by the user with net <spi0_clk_i_1>. This pin will not be connected as a part of interface connection <SPI_0>.
    ### ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O
    connect_bd_net /spi0_clk_o /sys_ps7/SPI0_SCLK_O
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/SPI0_SCLK_O> is being overridden by the user with net <sys_ps7_SPI0_SCLK_O>. This pin will not be connected as a part of interface connection <SPI_0>.
    ### ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I
    connect_bd_net /spi0_sdo_i /sys_ps7/SPI0_MOSI_I
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/SPI0_MOSI_I> is being overridden by the user with net <spi0_sdo_i_1>. This pin will not be connected as a part of interface connection <SPI_0>.
    ### ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O
    connect_bd_net /spi0_sdo_o /sys_ps7/SPI0_MOSI_O
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/SPI0_MOSI_O> is being overridden by the user with net <sys_ps7_SPI0_MOSI_O>. This pin will not be connected as a part of interface connection <SPI_0>.
    ### ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I
    connect_bd_net /spi0_sdi_i /sys_ps7/SPI0_MISO_I
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/SPI0_MISO_I> is being overridden by the user with net <spi0_sdi_i_1>. This pin will not be connected as a part of interface connection <SPI_0>.
    ### ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O
    connect_bd_net /spi1_csn_2_o /sys_ps7/SPI1_SS2_O
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/SPI1_SS2_O> is being overridden by the user with net <sys_ps7_SPI1_SS2_O>. This pin will not be connected as a part of interface connection <SPI_1>.
    ### ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O
    connect_bd_net /spi1_csn_1_o /sys_ps7/SPI1_SS1_O
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/SPI1_SS1_O> is being overridden by the user with net <sys_ps7_SPI1_SS1_O>. This pin will not be connected as a part of interface connection <SPI_1>.
    ### ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O
    connect_bd_net /spi1_csn_0_o /sys_ps7/SPI1_SS_O
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/SPI1_SS_O> is being overridden by the user with net <sys_ps7_SPI1_SS_O>. This pin will not be connected as a part of interface connection <SPI_1>.
    ### ad_connect spi1_csn_i sys_ps7/SPI1_SS_I
    connect_bd_net /spi1_csn_i /sys_ps7/SPI1_SS_I
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/SPI1_SS_I> is being overridden by the user with net <spi1_csn_i_1>. This pin will not be connected as a part of interface connection <SPI_1>.
    ### ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I
    connect_bd_net /spi1_clk_i /sys_ps7/SPI1_SCLK_I
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/SPI1_SCLK_I> is being overridden by the user with net <spi1_clk_i_1>. This pin will not be connected as a part of interface connection <SPI_1>.
    ### ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O
    connect_bd_net /spi1_clk_o /sys_ps7/SPI1_SCLK_O
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/SPI1_SCLK_O> is being overridden by the user with net <sys_ps7_SPI1_SCLK_O>. This pin will not be connected as a part of interface connection <SPI_1>.
    ### ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I
    connect_bd_net /spi1_sdo_i /sys_ps7/SPI1_MOSI_I
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/SPI1_MOSI_I> is being overridden by the user with net <spi1_sdo_i_1>. This pin will not be connected as a part of interface connection <SPI_1>.
    ### ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O
    connect_bd_net /spi1_sdo_o /sys_ps7/SPI1_MOSI_O
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/SPI1_MOSI_O> is being overridden by the user with net <sys_ps7_SPI1_MOSI_O>. This pin will not be connected as a part of interface connection <SPI_1>.
    ### ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I
    connect_bd_net /spi1_sdi_i /sys_ps7/SPI1_MISO_I
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps7/SPI1_MISO_I> is being overridden by the user with net <spi1_sdi_i_1>. This pin will not be connected as a part of interface connection <SPI_1>.
    ### ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P
    connect_bd_net /sys_concat_intc/dout /sys_ps7/IRQ_F2P
    ### ad_connect sys_concat_intc/In15 ps_intr_15
    connect_bd_net /sys_concat_intc/In15 /ps_intr_15
    ### ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
    connect_bd_net /sys_concat_intc/In14 /axi_iic_main/iic2intc_irpt
    ### ad_connect sys_concat_intc/In13 ps_intr_13
    connect_bd_net /sys_concat_intc/In13 /ps_intr_13
    ### ad_connect sys_concat_intc/In12 ps_intr_12
    connect_bd_net /sys_concat_intc/In12 /ps_intr_12
    ### ad_connect sys_concat_intc/In11 ps_intr_11
    connect_bd_net /sys_concat_intc/In11 /ps_intr_11
    ### ad_connect sys_concat_intc/In10 ps_intr_10
    connect_bd_net /sys_concat_intc/In10 /ps_intr_10
    ### ad_connect sys_concat_intc/In9 ps_intr_09
    connect_bd_net /sys_concat_intc/In9 /ps_intr_09
    ### ad_connect sys_concat_intc/In8 ps_intr_08
    connect_bd_net /sys_concat_intc/In8 /ps_intr_08
    ### ad_connect sys_concat_intc/In7 ps_intr_07
    connect_bd_net /sys_concat_intc/In7 /ps_intr_07
    ### ad_connect sys_concat_intc/In6 ps_intr_06
    connect_bd_net /sys_concat_intc/In6 /ps_intr_06
    ### ad_connect sys_concat_intc/In5 ps_intr_05
    connect_bd_net /sys_concat_intc/In5 /ps_intr_05
    ### ad_connect sys_concat_intc/In4 ps_intr_04
    connect_bd_net /sys_concat_intc/In4 /ps_intr_04
    ### ad_connect sys_concat_intc/In3 ps_intr_03
    connect_bd_net /sys_concat_intc/In3 /ps_intr_03
    ### ad_connect sys_concat_intc/In2 ps_intr_02
    connect_bd_net /sys_concat_intc/In2 /ps_intr_02
    ### ad_connect sys_concat_intc/In1 ps_intr_01
    connect_bd_net /sys_concat_intc/In1 /ps_intr_01
    ### ad_connect sys_concat_intc/In0 ps_intr_00
    connect_bd_net /sys_concat_intc/In0 /ps_intr_00
    ### ad_cpu_interconnect 0x41600000 axi_iic_main
    connect_bd_net -net /sys_cpu_clk /sys_ps7/M_AXI_GP0_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/ACLK
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/S00_ACLK
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/S00_ARESETN
    connect_bd_intf_net /axi_cpu_interconnect/S00_AXI /sys_ps7/M_AXI_GP0
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M00_ACLK
    connect_bd_net -net /sys_cpu_clk /axi_iic_main/s_axi_aclk
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M00_ARESETN
    connect_bd_net -net /sys_cpu_resetn /axi_iic_main/s_axi_aresetn
    connect_bd_intf_net /axi_cpu_interconnect/M00_AXI /axi_iic_main/S_AXI
    ### create_bd_port -dir O enable
    ### create_bd_port -dir O txnrx
    ### create_bd_port -dir I up_enable
    ### create_bd_port -dir I up_txnrx
    ### create_bd_port -dir O tdd_sync_o
    ### create_bd_port -dir I tdd_sync_i
    ### create_bd_port -dir O tdd_sync_t
    ### create_bd_port -dir I gps_pps
    ### ad_ip_instance axi_ad9361 axi_ad9361
    ### ad_ip_parameter axi_ad9361 CONFIG.ID 0
    ### ad_ip_parameter axi_ad9361 CONFIG.DAC_IODELAY_ENABLE 1
    ### ad_connect sys_200m_clk axi_ad9361/delay_clk
    connect_bd_net -net /sys_200m_clk /axi_ad9361/delay_clk
    ### ad_connect axi_ad9361/l_clk axi_ad9361/clk
    connect_bd_net /axi_ad9361/l_clk /axi_ad9361/clk
    ### ad_connect enable axi_ad9361/enable
    connect_bd_net /enable /axi_ad9361/enable
    ### ad_connect txnrx axi_ad9361/txnrx
    connect_bd_net /txnrx /axi_ad9361/txnrx
    ### ad_connect up_enable axi_ad9361/up_enable
    connect_bd_net /up_enable /axi_ad9361/up_enable
    ### ad_connect up_txnrx axi_ad9361/up_txnrx
    connect_bd_net /up_txnrx /axi_ad9361/up_txnrx
    ### ad_ip_instance util_tdd_sync util_ad9361_tdd_sync
    ### ad_ip_parameter util_ad9361_tdd_sync CONFIG.TDD_SYNC_PERIOD 10000000
    ### ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk
    connect_bd_net -net /sys_cpu_clk /util_ad9361_tdd_sync/clk
    ### ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn
    connect_bd_net -net /sys_cpu_resetn /util_ad9361_tdd_sync/rstn
    ### ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
    connect_bd_net /util_ad9361_tdd_sync/sync_out /axi_ad9361/tdd_sync
    ### ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr
    connect_bd_net /util_ad9361_tdd_sync/sync_mode /axi_ad9361/tdd_sync_cntr
    ### ad_connect tdd_sync_t axi_ad9361/tdd_sync_cntr
    connect_bd_net /tdd_sync_t /axi_ad9361/tdd_sync_cntr
    ### ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out
    connect_bd_net /tdd_sync_o /util_ad9361_tdd_sync/sync_out
    ### ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in
    connect_bd_net /tdd_sync_i /util_ad9361_tdd_sync/sync_in
    ### ad_connect gps_pps axi_ad9361/gps_pps
    connect_bd_net /gps_pps /axi_ad9361/gps_pps
    ### ad_ip_instance xlconcat util_ad9361_divclk_sel_concat
    WARNING: [BD 41-1753] The name 'util_ad9361_divclk_sel_concat' you have specified is long. The Windows OS has path length limitations. It is recommended you use shorter names(less than 25 characters) to reduce the likelihood of issues when/if running on windows OS.
    ### ad_ip_parameter util_ad9361_divclk_sel_concat CONFIG.NUM_PORTS 2
    ### ad_connect axi_ad9361/adc_r1_mode util_ad9361_divclk_sel_concat/In0
    connect_bd_net /axi_ad9361/adc_r1_mode /util_ad9361_divclk_sel_concat/In0
    ### ad_connect axi_ad9361/dac_r1_mode util_ad9361_divclk_sel_concat/In1
    connect_bd_net /axi_ad9361/dac_r1_mode /util_ad9361_divclk_sel_concat/In1
    ### ad_ip_instance util_reduced_logic util_ad9361_divclk_sel
    ### ad_ip_parameter util_ad9361_divclk_sel CONFIG.C_SIZE 2
    ### ad_connect util_ad9361_divclk_sel_concat/dout util_ad9361_divclk_sel/Op1
    connect_bd_net /util_ad9361_divclk_sel_concat/dout /util_ad9361_divclk_sel/Op1
    ### ad_ip_instance util_clkdiv util_ad9361_divclk
    ### ad_connect util_ad9361_divclk_sel/Res util_ad9361_divclk/clk_sel
    connect_bd_net /util_ad9361_divclk_sel/Res /util_ad9361_divclk/clk_sel
    ### ad_connect axi_ad9361/l_clk util_ad9361_divclk/clk
    connect_bd_net /axi_ad9361/l_clk /util_ad9361_divclk/clk
    ### ad_ip_instance proc_sys_reset util_ad9361_divclk_reset
    ### ad_connect sys_rstgen/peripheral_aresetn util_ad9361_divclk_reset/ext_reset_in
    connect_bd_net /sys_rstgen/peripheral_aresetn /util_ad9361_divclk_reset/ext_reset_in
    ### ad_connect util_ad9361_divclk/clk_out util_ad9361_divclk_reset/slowest_sync_clk
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_divclk_reset/slowest_sync_clk
    ### ad_ip_instance util_wfifo util_ad9361_adc_fifo
    ### ad_ip_parameter util_ad9361_adc_fifo CONFIG.NUM_OF_CHANNELS 4
    ### ad_ip_parameter util_ad9361_adc_fifo CONFIG.DIN_ADDRESS_WIDTH 4
    ### ad_ip_parameter util_ad9361_adc_fifo CONFIG.DIN_DATA_WIDTH 16
    ### ad_ip_parameter util_ad9361_adc_fifo CONFIG.DOUT_DATA_WIDTH 16
    ### ad_connect axi_ad9361/l_clk util_ad9361_adc_fifo/din_clk
    connect_bd_net /axi_ad9361/l_clk /util_ad9361_adc_fifo/din_clk
    ### ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst
    connect_bd_net /axi_ad9361/rst /util_ad9361_adc_fifo/din_rst
    ### ad_connect util_ad9361_divclk/clk_out util_ad9361_adc_fifo/dout_clk
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_adc_fifo/dout_clk
    ### ad_connect util_ad9361_divclk_reset/peripheral_aresetn util_ad9361_adc_fifo/dout_rstn
    connect_bd_net /util_ad9361_divclk_reset/peripheral_aresetn /util_ad9361_adc_fifo/dout_rstn
    ### ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
    connect_bd_net /axi_ad9361/adc_enable_i0 /util_ad9361_adc_fifo/din_enable_0
    ### ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
    connect_bd_net /axi_ad9361/adc_valid_i0 /util_ad9361_adc_fifo/din_valid_0
    ### ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
    connect_bd_net /axi_ad9361/adc_data_i0 /util_ad9361_adc_fifo/din_data_0
    ### ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1
    connect_bd_net /axi_ad9361/adc_enable_q0 /util_ad9361_adc_fifo/din_enable_1
    ### ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1
    connect_bd_net /axi_ad9361/adc_valid_q0 /util_ad9361_adc_fifo/din_valid_1
    ### ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1
    connect_bd_net /axi_ad9361/adc_data_q0 /util_ad9361_adc_fifo/din_data_1
    ### ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2
    connect_bd_net /axi_ad9361/adc_enable_i1 /util_ad9361_adc_fifo/din_enable_2
    ### ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2
    connect_bd_net /axi_ad9361/adc_valid_i1 /util_ad9361_adc_fifo/din_valid_2
    ### ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2
    connect_bd_net /axi_ad9361/adc_data_i1 /util_ad9361_adc_fifo/din_data_2
    ### ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3
    connect_bd_net /axi_ad9361/adc_enable_q1 /util_ad9361_adc_fifo/din_enable_3
    ### ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3
    connect_bd_net /axi_ad9361/adc_valid_q1 /util_ad9361_adc_fifo/din_valid_3
    ### ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3
    connect_bd_net /axi_ad9361/adc_data_q1 /util_ad9361_adc_fifo/din_data_3
    ### ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
    connect_bd_net /util_ad9361_adc_fifo/din_ovf /axi_ad9361/adc_dovf
    ### ad_ip_instance util_cpack util_ad9361_adc_pack
    ### ad_ip_parameter util_ad9361_adc_pack CONFIG.NUM_OF_CHANNELS 4
    ### ad_ip_parameter util_ad9361_adc_pack CONFIG.CHANNEL_DATA_WIDTH 16
    ### ad_connect util_ad9361_divclk/clk_out util_ad9361_adc_pack/adc_clk
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_adc_pack/adc_clk
    ### ad_connect util_ad9361_divclk_reset/peripheral_reset util_ad9361_adc_pack/adc_rst
    connect_bd_net /util_ad9361_divclk_reset/peripheral_reset /util_ad9361_adc_pack/adc_rst
    ### ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_0 /util_ad9361_adc_pack/adc_enable_0
    ### ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0
    connect_bd_net /util_ad9361_adc_fifo/dout_valid_0 /util_ad9361_adc_pack/adc_valid_0
    ### ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0
    connect_bd_net /util_ad9361_adc_fifo/dout_data_0 /util_ad9361_adc_pack/adc_data_0
    ### ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_1 /util_ad9361_adc_pack/adc_enable_1
    ### ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1
    connect_bd_net /util_ad9361_adc_fifo/dout_valid_1 /util_ad9361_adc_pack/adc_valid_1
    ### ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1
    connect_bd_net /util_ad9361_adc_fifo/dout_data_1 /util_ad9361_adc_pack/adc_data_1
    ### ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_2 /util_ad9361_adc_pack/adc_enable_2
    ### ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2
    connect_bd_net /util_ad9361_adc_fifo/dout_valid_2 /util_ad9361_adc_pack/adc_valid_2
    ### ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2
    connect_bd_net /util_ad9361_adc_fifo/dout_data_2 /util_ad9361_adc_pack/adc_data_2
    ### ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3
    connect_bd_net /util_ad9361_adc_fifo/dout_enable_3 /util_ad9361_adc_pack/adc_enable_3
    ### ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3
    connect_bd_net /util_ad9361_adc_fifo/dout_valid_3 /util_ad9361_adc_pack/adc_valid_3
    ### ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3
    connect_bd_net /util_ad9361_adc_fifo/dout_data_3 /util_ad9361_adc_pack/adc_data_3
    ### ad_ip_instance axi_dmac axi_ad9361_adc_dma
    ### ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_SRC 2
    ### ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_DEST 0
    ### ad_ip_parameter axi_ad9361_adc_dma CONFIG.CYCLIC 0
    ### ad_ip_parameter axi_ad9361_adc_dma CONFIG.SYNC_TRANSFER_START 1
    ### ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_SRC 0
    ### ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 0
    ### ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0
    ### ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 64
    ### ad_connect util_ad9361_divclk/clk_out axi_ad9361_adc_dma/fifo_wr_clk
    connect_bd_net /util_ad9361_divclk/clk_out /axi_ad9361_adc_dma/fifo_wr_clk
    ### ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en
    connect_bd_net /util_ad9361_adc_pack/adc_valid /axi_ad9361_adc_dma/fifo_wr_en
    WARNING: [BD 41-1306] The connection to interface pin </axi_ad9361_adc_dma/fifo_wr_en> is being overridden by the user with net <util_ad9361_adc_pack_adc_valid>. This pin will not be connected as a part of interface connection <fifo_wr>.
    ### ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
    connect_bd_net /util_ad9361_adc_pack/adc_sync /axi_ad9361_adc_dma/fifo_wr_sync
    WARNING: [BD 41-1306] The connection to interface pin </axi_ad9361_adc_dma/fifo_wr_sync> is being overridden by the user with net <util_ad9361_adc_pack_adc_sync>. This pin will not be connected as a part of interface connection <fifo_wr>.
    ### ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
    connect_bd_net /util_ad9361_adc_pack/adc_data /axi_ad9361_adc_dma/fifo_wr_din
    WARNING: [BD 41-1306] The connection to interface pin </axi_ad9361_adc_dma/fifo_wr_din> is being overridden by the user with net <util_ad9361_adc_pack_adc_data>. This pin will not be connected as a part of interface connection <fifo_wr>.
    ### ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
    connect_bd_net /axi_ad9361_adc_dma/fifo_wr_overflow /util_ad9361_adc_fifo/dout_ovf
    WARNING: [BD 41-1306] The connection to interface pin </axi_ad9361_adc_dma/fifo_wr_overflow> is being overridden by the user with net <axi_ad9361_adc_dma_fifo_wr_overflow>. This pin will not be connected as a part of interface connection <fifo_wr>.
    ### ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_adc_dma/m_dest_axi_aresetn
    ### ad_ip_instance util_rfifo axi_ad9361_dac_fifo
    ### ad_ip_parameter axi_ad9361_dac_fifo CONFIG.DIN_DATA_WIDTH 16
    ### ad_ip_parameter axi_ad9361_dac_fifo CONFIG.DOUT_DATA_WIDTH 16
    ### ad_ip_parameter axi_ad9361_dac_fifo CONFIG.DIN_ADDRESS_WIDTH 4
    ### ad_connect axi_ad9361/l_clk axi_ad9361_dac_fifo/dout_clk
    connect_bd_net /axi_ad9361/l_clk /axi_ad9361_dac_fifo/dout_clk
    ### ad_connect axi_ad9361/rst axi_ad9361_dac_fifo/dout_rst
    connect_bd_net /axi_ad9361/rst /axi_ad9361_dac_fifo/dout_rst
    ### ad_connect util_ad9361_divclk/clk_out axi_ad9361_dac_fifo/din_clk
    connect_bd_net /util_ad9361_divclk/clk_out /axi_ad9361_dac_fifo/din_clk
    ### ad_connect util_ad9361_divclk_reset/peripheral_aresetn axi_ad9361_dac_fifo/din_rstn
    connect_bd_net /util_ad9361_divclk_reset/peripheral_aresetn /axi_ad9361_dac_fifo/din_rstn
    ### ad_connect axi_ad9361_dac_fifo/dout_enable_0 axi_ad9361/dac_enable_i0
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_0 /axi_ad9361/dac_enable_i0
    ### ad_connect axi_ad9361_dac_fifo/dout_valid_0 axi_ad9361/dac_valid_i0
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_0 /axi_ad9361/dac_valid_i0
    ### ad_connect axi_ad9361_dac_fifo/dout_data_0 axi_ad9361/dac_data_i0
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_0 /axi_ad9361/dac_data_i0
    ### ad_connect axi_ad9361_dac_fifo/dout_enable_1 axi_ad9361/dac_enable_q0
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_1 /axi_ad9361/dac_enable_q0
    ### ad_connect axi_ad9361_dac_fifo/dout_valid_1 axi_ad9361/dac_valid_q0
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_1 /axi_ad9361/dac_valid_q0
    ### ad_connect axi_ad9361_dac_fifo/dout_data_1 axi_ad9361/dac_data_q0
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_1 /axi_ad9361/dac_data_q0
    ### ad_connect axi_ad9361_dac_fifo/dout_enable_2 axi_ad9361/dac_enable_i1
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_2 /axi_ad9361/dac_enable_i1
    ### ad_connect axi_ad9361_dac_fifo/dout_valid_2 axi_ad9361/dac_valid_i1
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_2 /axi_ad9361/dac_valid_i1
    ### ad_connect axi_ad9361_dac_fifo/dout_data_2 axi_ad9361/dac_data_i1
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_2 /axi_ad9361/dac_data_i1
    ### ad_connect axi_ad9361_dac_fifo/dout_enable_3 axi_ad9361/dac_enable_q1
    connect_bd_net /axi_ad9361_dac_fifo/dout_enable_3 /axi_ad9361/dac_enable_q1
    ### ad_connect axi_ad9361_dac_fifo/dout_valid_3 axi_ad9361/dac_valid_q1
    connect_bd_net /axi_ad9361_dac_fifo/dout_valid_3 /axi_ad9361/dac_valid_q1
    ### ad_connect axi_ad9361_dac_fifo/dout_data_3 axi_ad9361/dac_data_q1
    connect_bd_net /axi_ad9361_dac_fifo/dout_data_3 /axi_ad9361/dac_data_q1
    ### ad_connect axi_ad9361_dac_fifo/dout_unf axi_ad9361/dac_dunf
    connect_bd_net /axi_ad9361_dac_fifo/dout_unf /axi_ad9361/dac_dunf
    ### ad_ip_instance util_upack util_ad9361_dac_upack
    ### ad_ip_parameter util_ad9361_dac_upack CONFIG.NUM_OF_CHANNELS 4
    ### ad_ip_parameter util_ad9361_dac_upack CONFIG.CHANNEL_DATA_WIDTH 16
    ### ad_connect util_ad9361_divclk/clk_out util_ad9361_dac_upack/dac_clk
    connect_bd_net /util_ad9361_divclk/clk_out /util_ad9361_dac_upack/dac_clk
    ### ad_connect util_ad9361_dac_upack/dac_enable_0 axi_ad9361_dac_fifo/din_enable_0
    connect_bd_net /util_ad9361_dac_upack/dac_enable_0 /axi_ad9361_dac_fifo/din_enable_0
    ### ad_connect util_ad9361_dac_upack/dac_valid_0 axi_ad9361_dac_fifo/din_valid_0
    connect_bd_net /util_ad9361_dac_upack/dac_valid_0 /axi_ad9361_dac_fifo/din_valid_0
    ### ad_connect util_ad9361_dac_upack/dac_valid_out_0 axi_ad9361_dac_fifo/din_valid_in_0
    connect_bd_net /util_ad9361_dac_upack/dac_valid_out_0 /axi_ad9361_dac_fifo/din_valid_in_0
    ### ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361_dac_fifo/din_data_0
    connect_bd_net /util_ad9361_dac_upack/dac_data_0 /axi_ad9361_dac_fifo/din_data_0
    ### ad_connect util_ad9361_dac_upack/dac_enable_1 axi_ad9361_dac_fifo/din_enable_1
    connect_bd_net /util_ad9361_dac_upack/dac_enable_1 /axi_ad9361_dac_fifo/din_enable_1
    ### ad_connect util_ad9361_dac_upack/dac_valid_1 axi_ad9361_dac_fifo/din_valid_1
    connect_bd_net /util_ad9361_dac_upack/dac_valid_1 /axi_ad9361_dac_fifo/din_valid_1
    ### ad_connect util_ad9361_dac_upack/dac_valid_out_1 axi_ad9361_dac_fifo/din_valid_in_1
    connect_bd_net /util_ad9361_dac_upack/dac_valid_out_1 /axi_ad9361_dac_fifo/din_valid_in_1
    ### ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361_dac_fifo/din_data_1
    connect_bd_net /util_ad9361_dac_upack/dac_data_1 /axi_ad9361_dac_fifo/din_data_1
    ### ad_connect util_ad9361_dac_upack/dac_enable_2 axi_ad9361_dac_fifo/din_enable_2
    connect_bd_net /util_ad9361_dac_upack/dac_enable_2 /axi_ad9361_dac_fifo/din_enable_2
    ### ad_connect util_ad9361_dac_upack/dac_valid_2 axi_ad9361_dac_fifo/din_valid_2
    connect_bd_net /util_ad9361_dac_upack/dac_valid_2 /axi_ad9361_dac_fifo/din_valid_2
    ### ad_connect util_ad9361_dac_upack/dac_valid_out_2 axi_ad9361_dac_fifo/din_valid_in_2
    connect_bd_net /util_ad9361_dac_upack/dac_valid_out_2 /axi_ad9361_dac_fifo/din_valid_in_2
    ### ad_connect util_ad9361_dac_upack/dac_data_2 axi_ad9361_dac_fifo/din_data_2
    connect_bd_net /util_ad9361_dac_upack/dac_data_2 /axi_ad9361_dac_fifo/din_data_2
    ### ad_connect util_ad9361_dac_upack/dac_enable_3 axi_ad9361_dac_fifo/din_enable_3
    connect_bd_net /util_ad9361_dac_upack/dac_enable_3 /axi_ad9361_dac_fifo/din_enable_3
    ### ad_connect util_ad9361_dac_upack/dac_valid_3 axi_ad9361_dac_fifo/din_valid_3
    connect_bd_net /util_ad9361_dac_upack/dac_valid_3 /axi_ad9361_dac_fifo/din_valid_3
    ### ad_connect util_ad9361_dac_upack/dac_valid_out_3 axi_ad9361_dac_fifo/din_valid_in_3
    connect_bd_net /util_ad9361_dac_upack/dac_valid_out_3 /axi_ad9361_dac_fifo/din_valid_in_3
    ### ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361_dac_fifo/din_data_3
    connect_bd_net /util_ad9361_dac_upack/dac_data_3 /axi_ad9361_dac_fifo/din_data_3
    ### ad_ip_instance axi_dmac axi_ad9361_dac_dma
    ### ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_SRC 0
    ### ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_DEST 2
    ### ad_ip_parameter axi_ad9361_dac_dma CONFIG.CYCLIC 1
    ### ad_ip_parameter axi_ad9361_dac_dma CONFIG.SYNC_TRANSFER_START 0
    WARNING: [BD 41-721] Attempt to set value '0' on disabled parameter 'SYNC_TRANSFER_START' of cell '/axi_ad9361_dac_dma' is ignored
    ### ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 0
    ### ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 1
    ### ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0
    ### ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 64
    ### ad_connect util_ad9361_divclk/clk_out axi_ad9361_dac_dma/fifo_rd_clk
    connect_bd_net /util_ad9361_divclk/clk_out /axi_ad9361_dac_dma/fifo_rd_clk
    ### ad_connect axi_ad9361_dac_dma/fifo_rd_en util_ad9361_dac_upack/dac_valid
    connect_bd_net /axi_ad9361_dac_dma/fifo_rd_en /util_ad9361_dac_upack/dac_valid
    WARNING: [BD 41-1306] The connection to interface pin </axi_ad9361_dac_dma/fifo_rd_en> is being overridden by the user with net <util_ad9361_dac_upack_dac_valid>. This pin will not be connected as a part of interface connection <fifo_rd>.
    ### ad_connect axi_ad9361_dac_dma/fifo_rd_dout util_ad9361_dac_upack/dac_data
    connect_bd_net /axi_ad9361_dac_dma/fifo_rd_dout /util_ad9361_dac_upack/dac_data
    WARNING: [BD 41-1306] The connection to interface pin </axi_ad9361_dac_dma/fifo_rd_dout> is being overridden by the user with net <axi_ad9361_dac_dma_fifo_rd_dout>. This pin will not be connected as a part of interface connection <fifo_rd>.
    ### ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
    connect_bd_net -net /sys_cpu_resetn /axi_ad9361_dac_dma/m_src_axi_aresetn
    ### ad_cpu_interconnect 0x79020000 axi_ad9361
    WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins -filter {MODE == Slave && VLNV == xilinx.com:interface:aximm_rtl:1.0} -of_objects /axi_ad9361'
    connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M01_ACLK
    connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M01_ARESETN
    connect_bd_intf_net /axi_cpu_interconnect/M01_AXI 
    ERROR: [BD 5-106] Arguments to the connect_bd_intf_net command cannot be empty.
    ERROR: [Common 17-39] 'connect_bd_intf_net' failed due to earlier errors.
    
        while executing
    "connect_bd_intf_net $m_name_1 $m_name_2"
        invoked from within
    "if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} {
        puts "connect_bd_intf_net $m_name_1 $m_name_2"
        connect_bd_intf_net $m_name_1 $m_name_2
    ..."
        (procedure "ad_connect" line 40)
        invoked from within
    "ad_connect axi_cpu_interconnect/${i_str}_AXI ${p_intf}"
        (procedure "ad_cpu_interconnect" line 127)
        invoked from within
    "ad_cpu_interconnect 0x79020000 axi_ad9361"
        (file "../common/adrv9361z7035_bd.tcl" line 380)
    
        while executing
    "source ../common/adrv9361z7035_bd.tcl"
        (file "system_bd.tcl" line 2)
    
        while executing
    "source system_bd.tcl"
        (procedure "adi_project_xilinx" line 98)
        invoked from within
    "adi_project_xilinx adrv9361z7035_ccfmc_lvds"
        (file "./system_project.tcl" line 7)
    update_compile_order -fileset sources_1

  • Hello  ,

    I looked deeper into this issue and it seems that we cannot offer support for partial reconfiguration at this moment. I can give you limited help in this direction, BUT I am not familiar with it, thus I cannot guarantee the success of this project.

    What branch did you use when building the project? I suppose master?
    If so, please use hdl_2021_r1 (and Vivado 2021.1) since this is the latest stable branch and the projects from here are tested and are working. The master branch is unstable.

    Can you open a console, go to the folder of your project and run make there? Like it's done here. And to tell me what you get.

    Afterwards, I would run adi_prcfg_project.tcl, but it needs some adaptations, since this is an old script and our projects have changed and tools also. Now we use Xilinx Vitis and not SDK anymore (here if you see, it creates SDK folders, and it has to be modified).

    After building the project, I think you should change the script to adapt it to our current structure.

    Regards,
    Iulia