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clock domain crossing in ADI HDL projects

Category: Hardware


We'd like to design an FPGA interface and control logic for AD9648 ADC. As I can see there is no reference design for this chip, but are for many others similar. Regarding the structure of these design, it seems common that the applied AXI interconnect clock/aresetn signals between the master CPU and slave peripherals are the same and the clock domain crossing and data transfer is implemented in the peripherals (hdl/up_xfer_cntrl.v at master · analogdevicesinc/hdl · GitHub).

Is there any specific reason that your designs prefer this method excusively instead of suppling AXI interconnect with different clocks and reset signals?

In other words, why don't we leave the interconnect to synchronize the different clock domains?

It would be great to have some explanation for this.