Post Go back to editing

DAQ2 latency for streaming

Category: Hardware
Product Number: AD-FMCDAQ2-EBZ
Software Version: 2019_r2_220331

Hi,

I am doing some experiments with FMCDAQ2 and the HDL reference implementation (ZCU102 board).

I found the streaming latency from HDL via AD9144 - loopback cable - AD9680 to HDL to be about 400 ns. Is this an realistic value?

The time is measured between axi_ad9144_tpl (outgoing) and axi_ad9680_tp (incoming), so there is no FIFO involved.

Thank you, and best regards,

Erik

Top Replies

    •   
    Jul 25, 2022 in reply to EHeinz689 +1 verified

    Hello  ,

    In my opinion the latency you measured is a reasonable one, as an example we measured the same 400ns round-trip TPL latency for another project with ad9081_fmca_ebz configured on the default…

Parents
  • Hello Erik!

    For this setup are you using no-os or Linux? Also how did you measure the delay between the two transport layers? Have you done any additional changes or are you using the original code from the 2019_r2 branch?

    Meanwhile I will try to simulate the JESD path for this block design and try to calculate the delay between the two TPLs.

    I will let you know what I'll get on my side! Kind regards!

    Filip.

  • Hello Filip,

    I am using the Linux environment, but I think this shouldn't matter here.

    I have modified the 2019_r2 HDL reference code a bit, but I didn't change the axi_ad9144_tpl -> axi_ad9144_jesd -> util_daq2_xcvr and util_daq2_xcvr -> axi_ad9680_jesd -> axi_ad9680_tpl parts, so the JESD parameters are still original.

    Basically, I introduced clocked gates before axi_ad9144_tpl and after axi_ad9680_tpl to be able to send and receive boxcar signals. AD9144 outputs are connected to AD9680 inputs. If I start both gates at the same time, I can see the delay between RX and TX in the output signal. This delay should include both JESD interfaces, the DAC and ADC itself, and the travel time on the cable.

    My question was just, what order of delay could be expected here and if 400 ns are a reasonable value.

    Best regards,

    Erik

Reply
  • Hello Filip,

    I am using the Linux environment, but I think this shouldn't matter here.

    I have modified the 2019_r2 HDL reference code a bit, but I didn't change the axi_ad9144_tpl -> axi_ad9144_jesd -> util_daq2_xcvr and util_daq2_xcvr -> axi_ad9680_jesd -> axi_ad9680_tpl parts, so the JESD parameters are still original.

    Basically, I introduced clocked gates before axi_ad9144_tpl and after axi_ad9680_tpl to be able to send and receive boxcar signals. AD9144 outputs are connected to AD9680 inputs. If I start both gates at the same time, I can see the delay between RX and TX in the output signal. This delay should include both JESD interfaces, the DAC and ADC itself, and the travel time on the cable.

    My question was just, what order of delay could be expected here and if 400 ns are a reasonable value.

    Best regards,

    Erik

Children
  • Moved the thread to the appropriate forum

  • Hello  ,

    In my opinion the latency you measured is a reasonable one, as an example we measured the same 400ns round-trip TPL latency for another project with ad9081_fmca_ebz configured on the default mode. You can also try this configuration with 4 lanes and 4 converters to see how that affects the latency: github.com/.../zynqmp-zcu102-rev10-fmcdaq2_m4_l4.dts

    Right now I'm working on measuring the latency on my side with the same setup!

    Regards,

    Filip.

  • Hello  ,

    You can also theoretically calculate a latency margin based on the JESD interface latency + the converters latency + couple of initialization clock cycles and some analog latencies.

    If you type the jesd_status command on your board you can see on the RX Link side some calculated latencies, those are the real jesd interface latencies for each lane. For example if we take the lane 0 we have 3 Multiframes(1 Multiframe = K*F = 32 * 1 Octets in our case) + 22 Octets(1 Octet = 1 ns because of the 10Gbps lane rate). So on the RX path we have (3*(32 * 1) + 22) octets = 118ns and we round that up to 128ns. We can assume the TX path takes approximately the same time, so we get a 256ns latency only from the JESD interface. 

    Next we want to calculate converters latencies, if we take the ADC(AD9680) data sheet we can see an end to end total latency calculated for our jesd configuration that is specified in the daq2 devicetree: adi-daq2.dtsiUsually for this project there is no decimation factor but we can still calculate a higher latency scenario.

    For the full bandwidth mode with DSP configured and with a decimation factor of 2. The latency will be 29 + 30 = 59 encode clocks = 59ns(Encode Clock frequency is 1000Mhz which is 1 ns) => 59ns.

    For the DAC(AD9144) we can see the interface delay of 17 PClock cycles(The PClock is the device clock with a 250Mhz equivalent to 4ns) so it's 68ns + the 1x interpolation filter which is 58 DAC clock cycles(a DAC clock frequency is 1000Mhz which is 1ns) =>68ns + 58ns =  126ns.

    If we add everything we will get approximately 256 + 59 + 126 = 441ns +/- Some initialization clock cycles and some analog delays. In conclusion depending on the jesd configuration and also on each converter configuration you can see how latency is affected.

    Hope this is helpful! 

    Best regards, 

    Filip.