I am doing some experiments with FMCDAQ2 and the HDL reference implementation (ZCU102 board).
I found the streaming latency from HDL via AD9144 - loopback cable - AD9680 to HDL to be about 400 ns. Is this an realistic value?
The time is measured between axi_ad9144_tpl (outgoing) and axi_ad9680_tp (incoming), so there is no FIFO involved.
Thank you, and best regards,