Custom Arria10 gx board with ad9361

Hi,

Can I please expect some reply regarding this query?

Hi,

If you have a custom design, which has all RX pins in a bank and all TX pins in a bank I believe you should be fine with the current IP.

For extra tips take a look at https://github.com/analogdevicesinc/hdl/pull/966.

Andrei

Hi,

I have a custom design where I am placing tx pins in Bank 3B and Rx pins in 3C.

Compiling the latest hdl-master using prime standard 18.1

Quartus gives me fitter error that it cannot place 5 periphery components due to conflicts with existing constraints (5 IO SERDES DPA)

Prince

I understand that the branch you mentioned is not supported. Requesting some directions in this approach .

Can you send me the source files?
It wold be easier for me if you use our flow to build your custom design.

Andrei

Hi, 

Using your source files only. 'hdl' repository from github..

If you can share your mail, I can send you the files that I am using

Prince

I took the hdl branch “fmcomm2_a10soc_bring_back” repo.

compiled the code for a10gx for ad9361..

Now, in ad9361.v —> for arria 10, it uses axi_ad9361_lvds_if_10.v

and in that it calls “altera serdes lvds” core wrapped as “intel serdes”. By default it is has mode parameter “Rx_No_DPA” set to “0”.

On compiling it in quartus, it gives a fitter error that it cannot fit 6 periphery components .

But if I set “Rx_No_DPA” to “1”, it compiles completely. 

I want to know, if this makes a difference to the performance of AD9361?

please let me know if anything is not clear.

Thanks

Prince

I took the hdl branch “fmcomm2_a10soc_bring_back” repo.

compiled the code for a10gx for ad9361..

Now, in ad9361.v —> for arria 10, it uses axi_ad9361_lvds_if_10.v

and in that it calls “altera serdes lvds” core wrapped as “intel serdes”. By default it is has mode parameter “Rx_No_DPA” set to “0”.

On compiling it in quartus, it gives a fitter error that it cannot fit 6 periphery components .

But if I set “Rx_No_DPA” to “1”, it compiles completely. 

I want to know, if this makes a difference to the performance of AD9361?

please let me know if anything is not clear.

Thanks

Prince