Post Go back to editing

ADRV9364-Z7020+BOB reference design in VHDL

Category: Software

Hi,

I built the HDL project for my ADRV9364-Z7020 device and ADRV1CRR-BOB carrier following this tutorial (https://wiki.analog.com/resources/fpga/docs/build).

When I open it with Vivado, all files are in Verilog. Is there a way to generate the project's files in VHDL instead?

Regards,

Fabio.