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issues related to reading data from ad7616

Category: Software
Product Number: AD7616 adc interface with zedboard
Software Version: Xilinx vivado 2019.1, HDL-2019_r2(for AD7616)

1)I am trying to read AD7616 in parallel mode. I have built the HDL and c drivers(No-OS branch) from the source code provided by Analog devices. I have modified the HDL so as to just keep the axi_ad7616 and its Fifo interface for the Dma. Rest part of the project i have removed. I am attaching the block diagram for the project.

After that, i am using this device in default mode where channel V0A and V0B should be read.
I When i am integrating this with sdk part and doing a cross triggering to check the data
converted by the ADC, I am finding there is no change on the data lines(adc_data) of the axi_ad7616 IP, however ADC valid, adc sync, adc busy all these signals are getting generated. I have attached the output.can someone help me?

2) Also when i am trying to read back the "range data" for Register A1, using the following command,
    uint16_t data;
    ad7616_par_read(dev, AD7616_REG_INPUT_RANGE_A1, &data);
    printf("Range = % d \n", data);

The output I am receiving is Range = 0,

However as per my input to init_param the value should be 255 right (since i have set range for ch V0A to V3A to AD7616_10V  )?,
 struct ad7616_init_param init_param = {
    /* SPI */
    .spi_param = &ad7616_spi_init,
    .offload_init_param = &spi_engine_offload_init_param,
    .reg_access_speed = 1000000,
    /* GPIO */
    .gpio_hw_rngsel0_param = NULL,
    .gpio_hw_rngsel1_param = NULL,
    .gpio_os0_param = NULL,
    .gpio_os1_param = NULL,
    .gpio_os2_param = NULL,
    .gpio_reset_param = &ad7616_gpio_reset,
    /* AXI Core */
    .core_baseaddr = AD7616_CORE_BASEADDR,
    /* Device Settings */
    .mode = AD7616_SW,
    .va = {AD7616_10V, AD7616_10V, AD7616_10V, AD7616_10V,
        AD7616_10V, AD7616_10V, AD7616_10V, AD7616_10V
    .vb = {
        AD7616_10V, AD7616_10V, AD7616_10V, AD7616_10V,
        AD7616_10V, AD7616_10V, AD7616_10V, AD7616_10V

    .osr = AD7616_OSR_0,
    .dcache_invalidate_range =
    (void (*)(uint32_t, uint32_t))Xil_DCacheInvalidateRange,

I have attached my block diagram as well as the cross triggering output window.

Any help will be highly appreciated. TIA

  • Hello,

    I've also put an ILA on the reference design from the main branch of HDL and No-OS and tested on hardware using Vivado 2021.1.

    I couldn't reproduce your issue in this case. As you may see, the adc_data changes along with the input data.

    I will also take a look into HDL_2019_R2 to see if I can reproduce the bug you mentioned. In the meantime could you try using the main branches and Vivado 2021.1?

    Kind Regards,


  • Hi,

    Thank u so much for giving dedicating time on this. I recreated the project from source files again. and this time my issue was resolved and working with vivado 2019.1 as well