I'm using the AD9213 ADC along with the ADI JESD IP. I have been able to successfully configure the part and link the JESD interface - FPGA Rx Link Layer is reporting "DATA" state. Thus has completed CGS and ILA phases. I then write 0x12 to AD9213 cfg register 0x505 in order to pipe in test data pattern 0x00/0xFF at the input of the serializer. Despite the FPGA Rx side reporting initial lane alignment and moving to "data" state, I can see from a data capture that not all lanes are actually aligned - each channel should be have a FF00 pattern.
I can reset and re-initialize the FMC and FPGA and it sometimes will link up (DATA state) and actually have all lanes aligned when using this check. After changing AD9213's x505 Test Mode register to 0x00 (ADC Data), I can finally get clean waveforms out of the TPL block.
Do you have any solution for this inconsistent lane alignment issue?
[locked by: imoldovan at 3:37 PM (GMT -5) on 10 Mar 2023]
[unlocked by: imoldovan at 3:38 PM (GMT -5) on 10 Mar 2023]