AD9213 using JESD204B Rx ADI IP: Lane Alignment Problem

Hello,

the alignment is done in the link layer,  on the capture you are showing the output of the physical layer. Is that correct? At physical layer each lane has a different latency,  that the link layer will iron out.

Please capture the output of the transport layer for the actual samples, or at least the output of the link layer. 

Thank you

Laszlo

Yes this is the output of physical layer (util_adc_0_xcvr). Correct me if I'm wrong, but the lane alignment is established during the ILA phase of the link initialization. Once ILA sequence is complete and the link layer (axi_ad9208_0_jesd) reports it is in "Data" status state (LINK_STATUS[1:0] = 3) the lanes should be aligned. 

Furthermore, I've gone through this exercise multiple times and can drive the FF00 pattern at any insertion point within the AD9213.

Whenever the lanes show a non-FF00 pattern when reg x505=x12, the output of Link layer shows a non-FF00 pattern when reg x505 = x22, the output of Transport layer shows a non-FF00 pattern when reg x505 = x02, and output of Transport layer shows garbage waveform when reg x505 = 00.

Although, whenever the lanes show a FF00 pattern when reg x505=x12, the output of Link layer shows a FF00 pattern when reg x505 = x22, and the output of Transport layer shows a FF00 pattern when reg x505 = x02, and output of Transport layer shows clean ADC sine-wave when reg x505 = 0x00.

crobbins said:

Correct me if I'm wrong, but the lane alignment is established during the ILA phase of the link initialization

Correct, lane alignment happens during ILAS but that happens in the link layer, and lanes are aligned across each other.

What you are seeing in the phy layer is the code group syncronization which is done with the help of the CGS /K28.5/ character to find the boundary of the 10 bit symbols in the serial stream. Those 10 bits are then decoded to 8 bits in the PHY. 

It looks the alignment at code group level is 'broken'.  That could happen  when the PHY is pulled out of reset and the alignment is enabled too early while the Tx side of the link is not yet sending the CGS characters and the CDR circuitry can't lock correctly and the channel goes to a bad state.   So ideally first the ADC should be configured then the Rx side of the link.

Can you detail what software are you using that manages this sequencing  ?

Thank you

Laszlo

Hi Laszlo,

There was an error in the PHY reset sequence of the JESD Rx link. I am using the ADI no-OS JESD drivers to configure FPGA JESD Rx side, and custom FSM to configure ADC JESD Tx via SPI. I can now power-up and link-up consistently. Thank you. 

Hi crobbins ,