Post Go back to editing

AD9213 using JESD204B Rx ADI IP: Lane Alignment Problem

Category: Hardware
Product Number: ad9213

Hi,

I'm using the AD9213 ADC along with the ADI JESD IP. I have been able to successfully configure the part and link the JESD interface - FPGA Rx Link Layer is reporting "DATA" state. Thus has completed CGS and ILA phases. I then write 0x12 to AD9213 cfg register 0x505 in order to pipe in test data pattern 0x00/0xFF at the input of the serializer. Despite the FPGA Rx side reporting initial lane alignment and moving to "data" state, I can see from a data capture that not all lanes are actually aligned - each channel should be have a FF00 pattern.

I can reset and re-initialize the FMC and FPGA and it sometimes will link up (DATA state) and actually have all lanes aligned when using this check. After changing AD9213's x505 Test Mode register to 0x00 (ADC Data), I can finally get clean waveforms out of the TPL block.

Do you have any solution for this inconsistent lane alignment issue?

Top Replies

    •   
    Jun 10, 2022 in reply to crobbins +2 verified
    Correct me if I'm wrong, but the lane alignment is established during the ILA phase of the link initialization

    Correct, lane alignment happens during ILAS but that happens in the link…

  • Hello,

    the alignment is done in the link layer,  on the capture you are showing the output of the physical layer. Is that correct? At physical layer each lane has a different latency,  that the link layer will iron out.

    Please capture the output of the transport layer for the actual samples, or at least the output of the link layer. 

    Thank you

    Laszlo

  • Yes this is the output of physical layer (util_adc_0_xcvr). Correct me if I'm wrong, but the lane alignment is established during the ILA phase of the link initialization. Once ILA sequence is complete and the link layer (axi_ad9208_0_jesd) reports it is in "Data" status state (LINK_STATUS[1:0] = 3) the lanes should be aligned. 

    Furthermore, I've gone through this exercise multiple times and can drive the FF00 pattern at any insertion point within the AD9213.

    Whenever the lanes show a non-FF00 pattern when reg x505=x12, the output of Link layer shows a non-FF00 pattern when reg x505 = x22, the output of Transport layer shows a non-FF00 pattern when reg x505 = x02, and output of Transport layer shows garbage waveform when reg x505 = 00.

    Although, whenever the lanes show a FF00 pattern when reg x505=x12, the output of Link layer shows a FF00 pattern when reg x505 = x22, and the output of Transport layer shows a FF00 pattern when reg x505 = x02, and output of Transport layer shows clean ADC sine-wave when reg x505 = 0x00.

  • Correct me if I'm wrong, but the lane alignment is established during the ILA phase of the link initialization

    Correct, lane alignment happens during ILAS but that happens in the link layer, and lanes are aligned across each other.

    What you are seeing in the phy layer is the code group syncronization which is done with the help of the CGS /K28.5/ character to find the boundary of the 10 bit symbols in the serial stream. Those 10 bits are then decoded to 8 bits in the PHY. 

    It looks the alignment at code group level is 'broken'.  That could happen  when the PHY is pulled out of reset and the alignment is enabled too early while the Tx side of the link is not yet sending the CGS characters and the CDR circuitry can't lock correctly and the channel goes to a bad state.   So ideally first the ADC should be configured then the Rx side of the link.

    Can you detail what software are you using that manages this sequencing  ?

    Thank you

    Laszlo

  • Hi Laszlo,

    There was an error in the PHY reset sequence of the JESD Rx link. I am using the ADI no-OS JESD drivers to configure FPGA JESD Rx side, and custom FSM to configure ADC JESD Tx via SPI. I can now power-up and link-up consistently. Thank you. 

  • Hi  ,

                      We are developing a driver for HTG_AD9213 with VCU118 for this we take AD9208_VCU118 as reference design. The JESD204B link status is DATA.The AD9213 ADC I'm using at 10Gsps sampling rate. The lane rate is 12.5Gbps, L=16, M=1(real ADC) , S =16 ,  F =2 , N = NP =16 ,  K =32, Full Bandwidth Mode, Subclass 1. fs = 10Gsps, FPGA_REF_CLK = lane rate / 40 = 312.5MHz ,  FPGA_DEV_CLK = lane rate/20 = 312.5MHz. 
             The JESD TPL outputs of ADC are constant and are not changing run to run in the ILA(chipscope). When we give an external input to ADC , the TPL(transport layer) outputs are not changing. The ADC data is fixed to a pattern. When we run test patterns using 0x505 register (Alternate checker board, 1/0 word toggle) , the TPL outputs of adc are observed correctly and here also the outputs are not changing run to run in the ILA. In the normal mode operation, the adc outputs are fixed to a particular pattern and are not changing run to run.Could you please guide me on this issue?
    Here I'm attaching the TPL outputs of ADC:
    Thanks in Advance
    Goli Ganesh