Frequency Hopping Example (RX-TX) for more than 8 profile ( adrv9361-z7035 & Adrv1crr-bob)

Question

Dear all, 
 Hopping IP has inserted in HDL_2019_r2 for adrv9361-z7035 and adrv1crr-bob . and I checked for 8x profile (Rx & Tx ) and its working correctly. Each profile covers 50MHz bandwidth ( total 8*50MHz).My application requires to scan wide bandwidth , detect peak and transmit that detected peak . For that it is necessary that rx and tx profile sync with each other . I did successfully for 8 profile . what is the starting point to do this more than 8x profile ? and any literature that how to calculate dwell time for x number of profiles.

travisfcollins · Answer

There is no documentation or examples on how to do this. 
 In theory, you need to first calibrate the VCO at each LO frequency and save off that data. This can be done with the fastlock profile control: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-transceiver/ad9361#fastlock_mode Once you have these values you need to load them during runtime. The ideal solution is to put a real-time SPI controller inside the FPGA fabric that can load in these profiles deterministically. 
 -Travis

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Frequency Hopping Example (RX-TX) for more than 8 profile ( adrv9361-z7035 & Adrv1crr-bob)

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