I am trying to bring up a JESD204B Link between a ZCU102 (TX) and AD9154 on the FMC-EBZ card (RX.) I am using the following parameters: LMFS = 8411, K=32, N=NP=16, subclass 0.
As a reference for the FPGA design, I took the analogdevices/hdl/projects/dac_fmc_ebz/zcu102 design and configured it for mode 0 with the AD9154. For the clocks, I am giving a 93.75MHz input on tx_refclk. According to the documentation for the transport and transmit IP's, the device clock that comes in needs to be 1/40 of the lane rate. From simulation I am observing that the lane rate is 1.875Gbps and thus I divide the output tx_out_clk_0 from the util_dac_jesd204_xcvr by 2 using a clocking wizard before feeding it into the link clock and device clock on the Transport and Transmit blocks.
I ran the simulation in which I configure the TX pipeline IP's according to the example testbench in analogdevices/testbenches/jesd_loopback project. Since my simulation only contains the TX side with no receiver, I externally toggle the SYNC line. When doing this I can see observe the TX side transition from stages 0 to 3 in the link procedure. I can see the lanes transmit the /K28.5/ character and then, if I manually toggle the SYNC line low and then sometime later high, the transceiver enters the ILAS stage and then the DATA stage.
On the DAC side, I am configuring the AD9154 with the following settings: 750MHz fed to the CLK_N/_P input, internal PLL off. The clocks comes from the onboard AD9516 which gives the 750MHz to the DAC and the 93.75MHz to the FPGA.
The issue I am observing is that on real hardware, the FPGA never progresses past the CGS stage. I verify the stage by looking at register 0x280 in the Transmit peripheral. Here are the register dumps from all 3 of the IP's (Transport, Transmit and Transceiver):
|Transport IP||Transmit IP||Transceiver IP|
|0x0000: 0x00090162||0x0000: 0x00010361||0x0000: 0x00110161|
|0x0004: 0x00000000||0x0004: 0x00000000||0x0004: 0x00000000|
|0x0008: 0x00000000||0x0008: 0x00000000||0x0008: 0x00000000|
|0x000c: 0x00000001||0x000c: 0x32303454||0x0010: 0x00000001|
|0x0010: 0x00000000||0x0010: 0x00000008||0x0014: 0x00000001|
|0x001c: 0x03041403||0x0014: 0x00000002||0x001c: 0x03041403|
|0x0040: 0x00000003||0x0018: 0x00000101||0x0020: 0x00001003|
|0x0044: 0x00000000||0x0080: 0x00000000||0x0024: 0x00180108|
|0x0048: 0x00000000||0x0084: 0x00000000||0x0040: 0x00000000|
|0x004c: 0x00000000||0x0088: 0x00000000||0x0044: 0x00000000|
|0x0050: 0x00000000||0x00c0: 0x00000000||0x0048: 0x00000000|
|0x0054: 0x00007803||0x00c4: 0x00000000||0x0060: 0x00000000|
|0x0058: 0x00000004||0x00c8: 0x00007803||0x0064: 0x00000000|
|0x005c: 0x00000001||0x00cc: 0x00000000||0x0068: 0x00000000|
|0x0060: 0x00000000||0x0100: 0x00000001||0x0080: 0x00000000|
|0x0068: 0x00000000||0x0104: 0x00000000||0x00a0: 0x00000000|
|0x0070: 0x00000000||0x0108: 0x00000001||0x00a4: 0x00000000|
|0x0074: 0x00020000||0x0200: 0x00000000||0x00a8: 0x00000000|
|0x0078: 0x00000000||0x0210: 0x0000001f||0x00ac: 0x00000000|
|0x007c: 0x00000000||0x0214: 0x00000000||0x00b0: 0x00000000|
|0x0088: 0x00000000||0x0218: 0x00000000||0x00b4: 0x00000000|
|0x00a0: 0x00000004||0x021c: 0x00000000||0x00b8: 0x00000000|
|0x00b8: 0x00000000||0x0240: 0x00000000||0x00bc: 0x00000000|
|0x00bc: 0x00000000||0x0244: 0x00000003||0x00c0: 0x00000008|
|0x0200: 0x00000000||0x0248: 0x00000000||0x00c4: 0x00000000|
|0x0204: 0x00000001||0x0280: 0x00000001||0x00c8: 0x00000000|
|0x0240: 0x01010804||0x0140: 0x00000352|
|0x0244: 0x00001010||0x0180: 0x00000000|
|0x0248: 0x00000000||0x0184: 0x00000000|
After reading these registers and configuring the FPGA PL, the clock AD9516 clock chip and the DAC, I took a high speed scope and probed the physical lanes coming into the DAC chip on the AD9154-DAC-FMC board. I probed the SYNC line and saw that it was indeed held low at around 200mV. I then probed the lanes and saw that they did not look right (there was no /K28.5/ character and the lane rate did not look correct either.) On the photos below, image 0 shows lane 0, image 1 shows lane 1 and image 2 shows lane 6 - the rest of the lanes look very similar to lane 0. From the simulation, the link is supposed to be running at 1.875Gbps but none of the images seem to show this. The timescale on the images is 500ps/box.
Here are the util_adxcvr_v1_0 settings that I am using:
It seems from the images that something about the transceiver isn't set up properly but it is not obvious to me what it is. In the transceiver, register 0x14 set to 1 indicates that PLL locked and things should be running but that does not seem to be the case. Should I be able to see the /K28.5/ characters clearly using an oscilloscope? Is there something else I can look at to debug this and understand the difference between the simulation and reality?
My understanding is that if the RX side keeps the SYNC low then the transmitter should be sending a continuous stream of /K28.5/ characters which I should be able to observe, right?
Thank you for your help,