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VCU118_AD9213 Interfacing Issues

Category: Software
Hi team,
              We are trying to develop the driver for AD9213 with VCU118. Since there is no reference design and API's for AD9213 , we take AD9208_VCU118 as a reference design. We are using AD9213 at 12.5Gbps lane rate with L=16, M=1, N=N' = 16, F=2, S=8, Fout =10Gsps.
              We are following the startup sequence in the datasheet to initialize the AD9213. We read and write the registers for AD9213 and it communicates with the FPGA. AD9231 PLL is locked but we are stuck in CGS state. What were the reasons for this CGS state? Could please guide us to drive JESD link status to "Data" state instead of this CGS state.


Thanks in Advance

Goli Ganesh


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  • Hello Goli Ganesh,

    Sorry I haven't replied in a while. We were trying to get the new version of the AD9213 Eval Board working on the VCU118 so we have something to experiment on our side. Although we have an HDL design, we haven't yet managed to update the software with the additional drivers required for the EVB. Until we have things working on our side, it's unlikely we can help debug designs with hardware we cannot test on.