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VCU118_AD9213 Interfacing Issues

Category: Software
Hi team,
              We are trying to develop the driver for AD9213 with VCU118. Since there is no reference design and API's for AD9213 , we take AD9208_VCU118 as a reference design. We are using AD9213 at 12.5Gbps lane rate with L=16, M=1, N=N' = 16, F=2, S=8, Fout =10Gsps.
              We are following the startup sequence in the datasheet to initialize the AD9213. We read and write the registers for AD9213 and it communicates with the FPGA. AD9231 PLL is locked but we are stuck in CGS state. What were the reasons for this CGS state? Could please guide us to drive JESD link status to "Data" state instead of this CGS state.


Thanks in Advance

Goli Ganesh


Parents Reply
  • Hi  ,

              I am using the below clock configurations for HTG_AD9213_VCU118.  Can you please verify whether I am configuring it correctly or not.

              L = 16, M =1 (real ADC) ,  N = NP = 16 , fout = 10Gsps , F = 2 , S = 16, HD = 0, JESD Subclass = 1.

    HMC7044 clkin freq = 122.88MHz , PLL2 frequency = 2457600000.

    FMC_REFCLK0 = 307.2MHz,  FMC_REFCLK1 = 307.2MHz

    Lane rate  = 12288.00MHz

    Lane rate /40 = 307.200MHz

    LMFC rate = 19.200MHz

     Sysref Divider Value  = 512

    ADF4371 RF16 frequency = 9830400000

    AD9213 PLL is Locked

    SYSREF captured : Yes

    SYSREF alignment error : No

    Link status : CGS

    Thanks in Advance

    Goli Ganesh