VCU118_AD9213 Interfacing Issues

Hello,

The AD9213 evaluation board doesn't have clocking onboard so there is no path to clock the trasceivers clocking input. How did you got around this ?

Regards,

Adrian

Hi AdrianC ,

Hi AdrianC ,

Hello,

I don't have access to that FMC board schematic. Is it something you can share ?

Regards,

Adrian

Hi AdrianC ,

           Here I am attaching the HTG AD9213 FMC board  Schematic.

https://drive.google.com/drive/folders/1gjMeuWKi18H41zhVwqu5rQ1X3AdprupG?usp=sharing

Thanks in Advance

Goli Ganesh

Hi AdrianC ,

          I am using the below clock configurations for HTG_AD9213_VCU118.  Can you please verify whether I am configuring it correctly or not.

          L = 16, M =1 (real ADC) ,  N = NP = 16 , fout = 10Gsps , F = 2 , S = 16, HD = 0, JESD Subclass = 1.

HMC7044 clkin freq = 122.88MHz , PLL2 frequency = 2457600000.

FMC_REFCLK0 = 307.2MHz,  FMC_REFCLK1 = 307.2MHz

Lane rate  = 12288.00MHz

Lane rate /40 = 307.200MHz

LMFC rate = 19.200MHz

 Sysref Divider Value  = 512

ADF4371 RF16 frequency = 9830400000

AD9213 PLL is Locked

SYSREF captured : Yes

SYSREF alignment error : No

Link status : CGS

Thanks in Advance

Goli Ganesh

Hello Goli Ganesh,

The configuration looks ok.

Are you using No-OS to configure the transceivers on the FPGA side ?

When you say you started from AD9208 design, you mean this one: AD9208-DUAL-EBZ HDL reference design [Analog Devices Wiki] ?

If you're using no-os, can you post the output of the run ?

Regards,

Adrian

Hi AdrianC ,

Hi AdrianC 

Hi AdrianC 

Hello Goli Ganesh,

Sorry I haven't replied in a while. We were trying to get the new version of the AD9213 Eval Board working on the VCU118 so we have something to experiment on our side. Although we have an HDL design, we haven't yet managed to update the software with the additional drivers required for the EVB. Until we have things working on our side, it's unlikely we can help debug designs with hardware we cannot test on.

Regards,

Adrian